Understanding Simultaneous Multithreading in Modern Processors

In course

This course explores techniques for exploiting instruction-level parallelism both statically and dynamically. It also addresses the generation of hardware accelerators from programming languages and investigates security issues related to microarchitectura ...

Description

This lecture discusses the concept of simultaneous multithreading (SMT) and its implementation in modern processors. It begins by reviewing the evolution of processor architectures, focusing on dynamically-scheduled architectures and the challenges they face, such as dependency issues and wasted issue slots. The instructor explains the need for multithreading to enhance performance by allowing multiple threads to share execution resources. Different multithreading techniques, including cycle-by-cycle and block interleaving, are introduced, highlighting their advantages and drawbacks. The lecture emphasizes the importance of efficient thread scheduling and the architectural requirements for SMT, such as multiple program counters and register files. The instructor also addresses the impact of SMT on single-thread performance and the trade-offs involved. Finally, the lecture covers real-world implementations of SMT, particularly in Intel's hyper-threading technology, showcasing its benefits and the minimal additional costs associated with its integration. Overall, the lecture provides a comprehensive overview of SMT and its significance in advancing processor performance.

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Instructor

Paolo Ienne

Paolo Ienne has been a Professor at the EPFL since 2000 and heads the Processor Architecture Laboratory (LAP). Prior to that, he worked for the Semiconductors Group of Siemens AG, Munich, Germany (which later became Infineon Technologies AG) where he was at the head of the Embedded Memories unit in the Design Libraries division. His research interests include various aspects of computer and processor architecture, FPGAs and reconfigurable computing, electronic design automation, and computer arithmetic. Ienne was a recipient of Best Paper Awards at the 20th, 24th, and 28th ACM/SIGDA International Symposia on Field-Programmable Gate Arrays (FPGA), in 2012, 2016 and 2020, at the 19th and 30th International Conference on Field-Programmable Logic and Applications (FPL), in 2009 and 2020, at the International Conference on Compilers, Architectures, and Synthesis for Embedded Systems (CASES), in 2007, and at the 40th Design Automation Conference (DAC), in 2003; many other papers have been candidates to Best Paper Awards in prestigious venues. He has served as general, programme, and topic chair of renown international conferences, including organizing in Lausanne the 26th International Conference on Field-Programmable Logic and Applications (FPL) in 2016. He serves on the steering committee of the IEEE Symposium on Computer Arithmetic (ARITH) and of the International Conference on Field-Programmable Logic and Applications (FPL). Ienne has guest edited a number of special issues and special sections on various topics for IEEE and ACM journals. He is regularly member of program committees of international workshops and conferences in the areas of design automation, computer architecture, embedded systems, compilers, FPGAs, and asynchronous design. He has been an associate editor of ACM Transactions on Architecture and Code Optimization (TACO), since 2015, of ACM Computing Surveys (CSUR), since 2014, and of ACM Transactions on Design Automation of Electronic Systems (TODAES) from 2011 to 2016.

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