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Concept

Multiplexer

Related publications (17)

Resource Sharing in Dataflow Circuits

Paolo Ienne, Andrea Guerrieri, Lana Josipovic, Axel Marmet

To achieve resource-efficient hardware designs, high-level synthesis (HLS) tools share (i.e., time-multiplex) functional units among operations of the same type. This optimization is typically performed in conjunction with operation scheduling to ensure th ...

Assoc Computing Machinery2023

Resource Sharing in Dataflow Circuits

Paolo Ienne, Andrea Guerrieri, Lana Josipovic, Axel Marmet

To achieve resource-efficient hardware designs, HLS tools share (i.e., time-multiplex) functional units among operations of the same type. This optimization is typically performed together with operation scheduling to ensure the best possible unit usage at ...

IEEE2022

Shrinking FPGA Static Power via Machine Learning-Based Power Gating and Enhanced Routing

Mirjana Stojilovic

Despite FPGAs rapidly evolving to support the requirements of the most demanding emerging applications, their high static power consumption, concentrated within the routing resources, still presents a major hurdle for low-power applications. Augmenting the ...

2021

Swap and Rotate: Lightweight Linear Layers for SPN-based Blockciphers

Serge Vaudenay, Francesco Regazzoni, Subhadeep Banik, Muhammed Fatih Balli

In CHES 2017, Jean et al. presented a paper on "Bit-Sliding" in which the authors proposed lightweight constructions for SPN based block ciphers like AES, PRESENT and SKINNY. The main idea behind these constructions was to reduce the length of the datapath ...

2020

Experimental Generation and Time Multiplexing of Data-Carrying Nyquist Sinc Shaped Channels from a Single Microresonator-based Kerr Frequency Comb

Tobias Kippenberg, Maxim Karpov, Martin Hubert Peter Pfeiffer, Arne Kordts, Yiming Cao, Fatemeh Alishahi

We experimentally achieve optical time multiplexing of multiple Nyquist channels. A single microresonator Kerr comb allows the generation of multiple Nyquist sinc shaped pulse trains. TDM of pulse trains are obtained through wavelength conversion inside a ...

IEEE2019

Toward a Full-Flexible and Fast-Prototyping TOF-PET Block Detector Based on TDC-on-FPGA

Edoardo Charbon, Esteban Venialgo Araujo

Typically, a time-of-flight (TOF) positron emission tomography (PET) block detector is built using application-specific integrated circuits (ASICs), since they integrate a high number of channels at a reasonable power consumption and into a small area. How ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2019

A programmable low-power ADC interface for an ISFET sweat sensor used in a wearable multi-sensing system

Maher Kayal, François Krummenacher, Evgenia Voulgari

An application specific integrated circuit (ASIC) named ANTIGONE (ANalog To dIGital cONvErter) was designed in AMS 0.35 mu m technology to interface with four Ion-sensitive field-effect transistor (ISFET) sensors and perform real-time monitoring of some bi ...

IEEE2019

LUT-Based Hierarchical Reversible Logic Synthesis

Giovanni De Micheli, Mathias Soeken

We present a synthesis framework to map logic networks into quantum circuits for quantum computing. The synthesis framework is based on lookup-table (urn networks, which play a key role in conventional logic synthesis. Establishing a connection between LUT ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2019

Optimization Opportunities in RRAM-based FPGA Architectures

Giovanni De Micheli, Pierre-Emmanuel Julien Marc Gaillardon, Xifan Tang

Static Random Access Memory (SRAM)-based routing multiplexers, whatever structure is employed, share a common limitation: their area, delay and power increase linearly with the input size. This property results in most SRAM-based FPGA architectures ...

IEEE2017

Physical Design Considerations of One-level RRAM-based Routing Multiplexers

Giovanni De Micheli, Pierre-Emmanuel Julien Marc Gaillardon, Xifan Tang, Edouard Giacomin

Resistive Random Access Memory (RRAM) technology opens the opportunity for granting both high-performance and low- power features to routing multiplexers. In this paper, we study the physical design considerations related to RRAM- based routing mult ...

ACM2017

Pattern-based fpga logic block and clustering algorithm

Giovanni De Micheli, Pierre-Emmanuel Julien Marc Gaillardon, Xifan Tang

A routing architecture for fast interconnections between Look-Up Tables (LUTs) in a group of Basic Logic Elements (BLEs), whereby a size of the group ranges from 1 to k+1, where k is the number of inputs of a LUT, and LUTs in the group are indexed from 1 t ...

2016

High-Voltage Tolerant Bi-State Self-Biasing Output Driver using Cascade Complementary Latches in Twin-well CMOS Technology

Scott Anthony Lindner

The design of a bi-state output buffer that can handle 5 times the supply voltage is presented. The use of self-biasing stacked devices driven by a cascade of complementary latches allows all devices to operate within the limits set by the technology, thus ...

Ieee2016

NEM Relay Design with Biconditional Binary Decision Diagrams

Giovanni De Micheli, Pierre-Emmanuel Julien Marc Gaillardon, Luca Gaetano Amarù, Winston Jason Haaswijk

In this paper, we present an improved design flow for nanoelectromechanical (NEM) relay-based combinational logic circuits. Six-terminal NEM relays can be programmed to act as 2-to-1 multiplexers. We can therefore use NEM relays to implement arbitrary comb ...

IEEE2015

Multiplex networks in metropolitan areas: generic features and local effects

Emanuele Strano

Most large cities are spanned by more than one transportation system. These different modes of transport have usually been studied separately: it is however important to understand the impact on urban systems of coupling different modes and we report in th ...

Royal Soc2015

Efficient MIMO transmission of PSK signals with a single-radio reconfigurable antenna

Julien Perruisseau-Carrier, Mohsen Yousefbeiki

Crucial developments to the recently introduced signal-space approach for multiplexing multiple data symbols using a single-radio switched antenna are presented. First, we introduce a general framework for expressing the spatial multiplexing relation of th ...

Institute of Electrical and Electronics Engineers2014

A 110mW 6 Bit 36GS/S Interleaved SAR ADC for 100 GBE Occupying 0.048mm2 in 32nm SOI CMOS

Yusuf Leblebici, Thomas Toifl, Lukas Kull

An area- and power-optimized asynchronous 32x interleaved SAR ADC achieving 36 GS/s at 110mW and 1V supply on the interleaver and 0.9V on the SAR ADCs is presented. The ADC features a 2-channel interleaver with data demultiplexing for enhanced bandwidth, a ...

2014

Pattern-reconfigurable built-in antenna for data multiplexing with a single radio

Julien Perruisseau-Carrier, Mohsen Yousefbeiki

Beam-space multiplexing has been demonstrated as a promising approach for transmitting multiple signals while using a single RF chain. This paper presents a novel beam-space antenna design that is very compact and integrated into a hypothetical portable pl ...

IEEE2013