Publication

Pattern-based fpga logic block and clustering algorithm

Giovanni De Micheli, Xifan Tang
2016
Patents

Abstract

A routing architecture for fast interconnections between Look-Up Tables (LUTs) in a group of Basic Logic Elements (BLEs), whereby a size of the group ranges from 1 to k+1, where k is the number of inputs of a LUT, and LUTs in the group are indexed from 1 to k+1, and whereby (a) an output of a LUTi, 1≦̸i≦̸k, connects to one of the inputs of routing multiplexers of LUTj, i

Official source

https://infoscience.epfl.ch/entities/publication/4fdbd911-f375-46b9-ae08-2c8d990e856f

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Pattern-based fpga logic block and clustering algorithm

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