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Concept

Peripheral Component Interconnect

Related publications (10)

Modeling and optimization of dedicated bus lanes space allocation in large networks with dynamic congestion

Nikolaos Geroliminis, Anastasios Kouvelas, Dimitrios Tsitsokas

Dedicated bus lanes provide a low cost and easily implementable strategy to improve transit service by minimizing congestion-related delays. Identifying the best spatial distribution of bus-only lanes in order to maximize traffic performance of an urban ne ...

2021

Evading Voltage-Based Intrusion Detection on Automotive CAN

Mathias Josef Payer

The controller area network (CAN) is widely adopted in modern automobiles to enable communications among in-vehicle electronic control units (ECUs). Lacking mainstream network security capabilities due to resource constraints, the CAN is susceptible to the ...

INTERNET SOC2021

GPU-accelerated data management under the test of time

Anastasia Ailamaki, Periklis Chrysogelos, Angelos Christos Anadiotis, Panagiotis Sioulas, Syed Mohammad Aunn Raza

GPUs are becoming increasingly popular in large scale data center installations due to their strong, embarrassingly parallel, processing capabilities. Data management systems are riding the wave by using GPUs to accelerate query execution, mainly for analy ...

2020

An Eight lanes 7Gb/s/pin Source Synchronous Single-Ended RX with Equalization and Far-End Crosstalk Cancellation for Backplane Channels

Yusuf Leblebici, Volkan Cevher, Alessandro Cevrero, Thomas Toifl, Lukas Kull, Cosimo Aprile

This paper presents a versatile crosstalk cancellation scheme for single-ended multi-lane backplane links. System-level investigations show that a scheme, which combines analog filters and decision-feedback crosstalk compensation on the receiver (RX) side ...

2018

Cost-Effective Design of Mesh-of-Tree Interconnect for Multi-Core Clusters with 3-D Stacked L2 Scratchpad Memory

Giovanni De Micheli, Luca Benini

3-D integrated circuits (3-D ICs) offer a promising solution to overcome the scaling limitations of 2-D ICs. However, using too many through-silicon-vias (TSVs) pose a negative impact on 3-D ICs due to the large overhead of TSV (e.g., large footprint and l ...

Institute of Electrical and Electronics Engineers2015

An Enhanced Design Methodology for Resonant Clock Trees

Giovanni De Micheli, Vasileios Pavlidis, Xifan Tang, Somayyeh Rahimian Omam

Clock distribution networks consume a considerable portion of the power dissipated by synchronous circuits. In conventional clock distribution networks, clock buffers are inserted to retain signal integrity along the long interconnects, which, in turn, sig ...

American Scientific Publishers2013

Scale-Out Processors

Pejman Lotfi Kamran

Global-scale online services, such as Google’s Web search and Facebook’s social networking, run in large-scale datacenters. Due to their massive scale, these services are designed to scale out (or distribute) their respective loads and datasets across thou ...

EPFL2013

Design of Resonant Clock Distribution Networks for 3-D Integrated Circuits

Giovanni De Micheli, Vasileios Pavlidis, Somayyeh Rahimian Omam

Designing a low power clock network in synchronous circuits is an important task. This requirement is stricter for 3-D circuits due to the increased power densities. Resonant clock networks are considered efficient low-power alternatives to conventional cl ...

Springer-Verlag2011

NoC Design and Implementation in 65 nm Technology

Giovanni De Micheli, David Atienza Alonso, Luca Benini, Srinivasan Murali, Federico Angiolini

As embedded computing evolves towards ever more powerful architectures, the challenge of properly interconnecting large numbers of on-chip computation blocks is becoming prominent. Networks-on-Chip (NoCs) have been proposed as a scalable solution to both p ...

2007

Towards a Unified Top-Down Design Flow for Fully-Differential Logic Blocks with Improved Speed and Noise Immunity

Yusuf Leblebici, Ilhan Hatirnaz

A new top-down design flow (RTL-to-GDSII) is proposed for achieving high-performance and noiseimmune designs consisting of differential logic blocks. The differential building blocks are based on the currentmode logic (CML), which offers true differentiali ...

2005