Advanced CMOS Circuits for Multi-Gb/s Links and 3D I/O Based on Through Silicon Via Technology

Chattez avec Graph Search

Posez n’importe quelle question sur les cours, conférences, exercices, recherches, actualités, etc. de l’EPFL ou essayez les exemples de questions ci-dessous.

AVERTISSEMENT : Le chatbot Graph n'est pas programmé pour fournir des réponses explicites ou catégoriques à vos questions. Il transforme plutôt vos questions en demandes API qui sont distribuées aux différents services informatiques officiellement administrés par l'EPFL. Son but est uniquement de collecter et de recommander des références pertinentes à des contenus que vous pouvez explorer pour vous aider à répondre à vos questions.

Wireless communication systems constantly estimate and equalize the channel to ensure reliable information transmission. The channel estimation not only facilitates effective communication, but also provides an opportunity to infer the physical environment ...

The dual-channel gate driver (D-GD) is widely employed in the industry to support the extensive adoption of half-bridge power modules. With the growing popularity of silicon-carbide (SiC) devices in medium-voltage scenarios known for their superior switchi ...

The radiation response of MOS transistors in a 22 nm Fully Depleted Silicon -On -Insulator (FDSOI) technology exposed to ultra -high total ionizing dose (TID) was investigated. Custom structures including n- and p -channel devices with different sizes and ...

We present an error correction code (ECC) decoder based on the Guessing Random Additive Noise Decoding (GRAND) with ABandonment (GRANDAB) algorithm for applications that require constant throughput and fixed decoding latency in the Gbps range. This high co ...

This article presents the design of an ultralow power short-range 57-66 GHz frequency-modulated continuous-wave (FMCW) radar. The transmitter (TX) path includes a BPSK modulator in order to implement a low-IF architecture and it is optimized for short-rang ...

The MOnolithic Stitched Sensor (MOSS) is a development prototype chip towards the ITS3 vertexing detector for the ALICE experiment at the LHC. Designed using a 65 nm CMOS Imaging technology, it aims at profiting from the stitching technique to construct a ...

Resistive Random Access Memories (ReRAMs) have been researched intensively in the last past decades as a promising alternatives technology for the next-generation non-volatile memory (NVM) devices. ReRAMâ s excellent performance properties such as high sw ...

Advanced CMOS Circuits for Multi-Gb/s Links and 3D I/O Based on Through Silicon Via Technology

Chattez avec Graph Search

Vital Signs and Human Activity Sensing with Wireless Systems

Advanced Dual-Channel Gate Driver with Short-circuit Protection for Series Connected Medium-Voltage SiC MOSFETs

Characteristics and ultra-high total ionizing dose response of 22nm fully depleted silicon-on-insulator

A GRANDAB Decoder with 8.48 Gbps Worst-Case Throughput in 65nm CMOS

An Ultralow Power Short-Range 60-GHz FMCW Radar in 22-nm FDSOI CMOS

Development of a Stitched Monolithic Pixel Sensor prototype (MOSS chip) towards the ITS3 upgrade of the ALICE Inner Tracking system

Material and Electrical study of HfO2-Based Resistive Random Access Memories (ReRAMs)