Unified prefetching into instruction cache and branch target buffer

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The increasing demand for computing power and the emergence of heterogeneous computing architectures have driven the exploration of innovative techniques to address current limitations in both the compute and memory subsystems. One such solution is the use ...

Driven by the demand for real-time processing and the need to minimize latency in AI algorithms, edge computing has experienced remarkable progress. Decision-making AI applications stand out for their heavy reliance on data-centric operations, predominantl ...

The spectral decomposition of cryptography into its life-giving components yields an interlaced network of tangential and orthogonal disciplines that are nonetheless invariably grounded by the same denominator: their implementation on commodity computing p ...

Side-channel disassembly attacks recover CPU instructions from power or electromagnetic side-channel traces measured during code execution. These attacks typically rely on physical access, proximity to the victim device, and high sampling rate measuring in ...

Analytical engines rely on in-memory data caching to avoid storage accesses and provide timely responses by keeping the most frequently accessed data in memory. Purely frequency- and time-based caching decisions, however, are a proxy of the expected query ...

Precise exceptions are a cornerstone of modern computing as they provide the abstraction of sequential instruction execution to programmers while accommodating microarchitectural optimizations. However, increasing compute capabilities in deep memory hierar ...

Virtual Memory (VM) is a critical programming abstraction that is widely used in various modern computing platforms. With the rise of datacenter computing and birth of planet-scale online services, the semantic and capacity requirements from memory have ev ...

Modern data center fabrics open the possibility of microsecond distributed applications, such as data stores and message queues. A challenging aspect of their development is to ensure that, besides being fast in the common case, these applications react fa ...

Context. A novel high-performance exact pair-counting toolkit called fast correlation function calculator (FCFC) is presented.Aims. With the rapid growth of modern cosmological datasets, the evaluation of correlation functions with observational and simula ...

A method for optimizing memory access for database operations is provided. The method may include performing a first database operation by at least executing a first instruction stream associated with the first database operation. The first database opera ...

A toric variety is called fibered if it can be represented as a total space of fibre bundle over toric base and with toric fiber. Fibered toric varieties form a special case of toric variety bundles. In this note we first give an introduction to the class ...

Accessing input data is a critical operation in data analytics: i) slow data access significantly degrades performance, and ii) storing everything in the fastest medium, i.e., memory, incurs high operational and hardware costs. Further, while GPUs offer in ...

High-performance branch target buffers (BTBs) and the L1I cache are key to high-performance front-end. Modern branch predictors are highly accurate, but with an increase in code footprint in modern-day server workloads, BTB and L1I misses are still frequen ...

Spatial understanding and communication are essential skills in human interaction. An adequate understanding of others' spatial perspectives can increase the quality of the interaction, both perceptually and cognitively. In this paper, we take the first st ...

Applications such as large-scale sparse linear algebra and graph analytics are challenging to accelerate on FPGAs due to the short irregular memory accesses, resulting in low cache hit rates. Nonblocking caches reduce the bandwidth required by misses by re ...

Analytical engines rely on in-memory caching to avoid disk accesses and provide timely responses by keeping the most frequently accessed data in memory. Purely frequency- & time-based caching decisions, however, are a proxy of the expected query execution ...

Given the need for efficient high-performance computing, computer architectures combining CPUs, GPUs, and FPGAs are nowadays prevalent. However, each of these components suffers from electrical-level security risks. Moving to heterogeneous systems, with th ...

Edge-computing requires high-performance energy-efficient embedded systems. Fixed-function or custom accelerators, such as FFT or FIR filter engines, are very efficient at implementing a particular functionality for a given set of constraints. However, the ...

As a unified data repository, data lake plays a vital role in enterprise data management and analysis. It composes the raw files into tables that are processed in-situ by various computation engines and applications. Therefore, the read performance of the ...

This thesis presents an efficient and extensible numerical software framework for real-time model-based control. We are motivated by complex and challenging mechatronic applications spanning from flight control of fixed-wing aircraft and thrust vector cont ...

Unified prefetching into instruction cache and branch target buffer

Chattez avec Graph Search

Intermediate Address Space: virtual memory optimization of heterogeneous architectures for cache-resident workloads

EdgeAI-Aware Design of In-Memory Computing Architectures

Green Cryptography and Other Optimisations

Instruction-Level Power Side-Channel Leakage Evaluation of Soft-Core CPUs on Shared FPGAs

HPCache: memory-efficient OLAP through proportional caching revisited

Imprecise Store Exceptions

Rebooting Virtual Memory with Midgard

uKharon: A Membership Service for Microsecond Applications

Fast correlation function calculator A high-performance pair-counting toolkit

Determining an optimum quantity of interleaved instruction streams of defined coroutines

FIBERED TORIC VARIETIES

HetCache: Synergising NVMe Storage and GPU acceleration for Memory-Efficient Analytics

Micro BTB: A High Performance and Storage Efficient Last-Level Branch Target Buffer for Servers

Do Children Adapt Their Perspective to a Robot When They Fail to Complete a Task?

Request, Coalesce, Serve, and Forget: Miss-Optimized Memory Systems for Bandwidth-Bound Cache-Unfriendly Applications on FPGAs

HPCache: Memory-Efficient OLAP Through Proportional Caching

Electrical-Level Attacks on CPUs, FPGAs, and GPUs: Survey and Implications in the Heterogeneous Era

VWR2A: A Very-Wide-Register Reconfigurable-Array Architecture for Low-Power Embedded Devices

Columnar Storage Optimization and Caching for Data Lakes

Real-Time Nonlinear Model Predictive Control for Fast Mechatronic Systems