Publications associées à Jitter Tolerance Analysis of Clock and Data Recovery Circuits using Matlab and VHDL-AMS

A Generalized Adjusted Min-Sum Decoder for 5G LDPC Codes: Algorithm and Implementation

Andreas Peter Burg, Alexios Konstantinos Balatsoukas Stimming, Yifei Shen, Yuqing Ren, Hassan Harb

5G New Radio (NR) has stringent demands on both performance and complexity for the design of low-density parity-check (LDPC) decoding algorithms and corresponding VLSI implementations. Furthermore, decoders must fully support the wide range of all 5G NR bl ...

Ieee-Inst Electrical Electronics Engineers Inc2024

Error estimates for SUPG-stabilised Dynamical Low Rank Approximations

Fabio Nobile, Thomas Simon Spencer Trigo Trindade

We perform an error analysis of a fully discretised Streamline Upwind Petrov Galerkin Dynamical Low Rank (SUPG-DLR) method for random time-dependent advection-dominated problems. The time integration scheme has a splitting-like nature, allowing for potenti ...

Springer Nature Switzerland2025

EdgeAI-Aware Design of In-Memory Computing Architectures

Marco Antonio Rios

Driven by the demand for real-time processing and the need to minimize latency in AI algorithms, edge computing has experienced remarkable progress. Decision-making AI applications stand out for their heavy reliance on data-centric operations, predominantl ...

EPFL2024

Low Power LDPC Decoding by Reliable Voltage Down-Scaling

Andreas Peter Burg

Low-Density Parity-Check (LDPC) decoder is among the power hungry building blocks of wireless communication systems. Voltage scaling down to Near-Threshold (NT) voltages substantially improves energy efficiency, in theory up 10x. However, tuning the voltag ...

IEEE2023

Analysis of the influence of errors in DNA-based image coding

Touradj Ebrahimi, Davi Nachtigall Lazzarotto, Michela Testolina

In the last decade, DNA has been increasingly investigated as an alternative medium for cold data storage, presenting several advantages over standard hard drives such as a higher density, longer lifespan and lower energy consumption. However, such coding ...

2023

Critical Schrodinger Cat Qubit

Vincenzo Savona, Luca Gravina, Fabrizio Minganti

Encoding quantum information onto bosonic systems is a promising route to quantum error correc-tion. In a cat code, this encoding relies on the confinement of the dynamics of the system onto the two-dimensional manifold spanned by Schrodinger cats of oppos ...

AMER PHYSICAL SOC2023

Discomfort glare from daylight: Influence of transmitted color and the eye's macular pigment

Sneha Jain

Designing architectural façades that allow sufficient daylight to create visually comfortable and pleasant environments is a challenging aspect of building design. It requires accounting for visual comfort and discomfort glare risks and understanding the f ...

EPFL2023

Time vs. Truth: Age-Distortion Tradeoffs and Strategies for Distributed Inference

Yunus Inan

In 1948, Claude Shannon laid the foundations of information theory, which grew out of a study to find the ultimate limits of source compression, and of reliable communication. Since then, information theory has proved itself not only as a quest to find the ...

EPFL2023

Quantization for Decentralized Learning Under Subspace Constraints

Ali H. Sayed, Roula Nassif, Stefan Vlaski, Marco Carpentiero

In this article, we consider decentralized optimization problems where agents have individual cost functions to minimize subject to subspace constraints that require the minimizers across the network to lie in low-dimensional subspaces. This constrained fo ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2023

Cascaded all-optical quantization employing step-size MMI and shape-optimized power splitter

Xiaowei Zhang, Ye Tian, Jian Wu, Jijun He

As a key unit of future high-throughput communications, optical analog to digital converter (OADC) with all-optical quantizer element that simultaneously possesses high resolution, large bandwidth and compact size is highly promising. A pending issue of co ...

ELSEVIER SCI LTD2023

An Error-Based Approximation Sensing Circuit for Event-Triggered Low-Power Wearable Sensors

David Atienza Alonso, Silvio Zanoli, Alexandre Sébastien Julien Levisse, Tomas Teijeiro Campo, Flavio Ponzina

Event-based sensors have the potential to optimize energy consumption at every stage in the signal processing pipeline, including data acquisition, transmission, processing, and storage. However, almost all state-of-the-art systems are still built upon th ...

2023

Ultra-High-Throughput EMS NB-LDPC Decoder with Full-Parallel Node Processing

Hassan Harb

This paper presents an ultra-high-throughput decoder architecture for NB-LDPC codes based on the Hybrid Extended Min-Sum algorithm. We introduce a new processing block that updates a check node and its associated variable nodes in a fully pipelined way, th ...

SPRINGER2022

List Ordered Statistics Decoders for Polar Codes

Andreas Peter Burg, Chuan Zhang, Yifei Shen

The de-facto standard decoding algorithm for polar codes, successive cancellation list (SCL) decoding, is a breadth-first search algorithm. By keeping a list of candidate codewords, SCL decoding improves the performance as the list size L increases. Howeve ...

IEEE2022

Dynamic SCL Decoder With Path-Flipping for 5G Polar Codes

Andreas Peter Burg, Alexios Konstantinos Balatsoukas Stimming, Chuan Zhang, Yifei Shen

Since polar were ratified as part of the 5G standard, low-complexity polar decoders with close-to-optimum error-rate performance have received significant attention. Compared to successive cancellation (SC) decoding, both SC list and SC flip decoding can i ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2022

Mismatched Decoding Reliability Function at Zero Rate

Marco Bondaschi

We derive an upper bound on the reliability function of mismatched decoding for zero-rate codes. The bound is based on a result by Komlos that shows the existence of a subcode with certain symmetry properties. The bound is shown to coincide with the expurg ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2022

Fast Sequence Repetition Node-Based Successive Cancellation List Decoding for Polar Codes

Andreas Peter Burg, Alexios Konstantinos Balatsoukas Stimming, Chuan Zhang, Andreas Toftegaard Kristensen, Yifei Shen, Yuqing Ren

Compared with the bit-wise successive cancellation list (SCL) decoding of polar codes, the node-based Fast SCL decoding significantly reduces the decoding latency by identifying special constituent codes and decoding these in parallel. To further reduce th ...

IEEE2022

Error Resilient In-Memory Computing Architecture for CNN Inference on the Edge

David Atienza Alonso, Giovanni Ansaloni, Alexandre Sébastien Julien Levisse, Flavio Ponzina, Marco Antonio Rios

The growing popularity of edge computing has fostered the development of diverse solutions to support Artificial Intelligence (AI) in energy-constrained devices. Nonetheless, comparatively few efforts have focused on the resiliency exhibited by AI workload ...

2022

A Low-Complexity LoRa Synchronization Algorithm Robust to Sampling Time Offsets

Orion Afisiadis, Mathieu Pierre Xhonneux

LoRaWAN is nowadays one of the most popular protocols for low-power Internet of Things communications. Although its physical layer, namely LoRa, has been thoroughly studied in the literature, aspects related to the synchronization of LoRa receivers have re ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2022

Humans are Poor Few-Shot Classifiers for Sentinel-2 Land Cover

Devis Tuia, Marc Conrad Russwurm

Learning to predict accurately from a few data samples is a central challenge in modern data-hungry machine learning. On natural images, human vision typically outperforms deep learning approaches on few-shot learning. However, we hypothesize that aerial a ...

IEEE2022

Optimizing Lattice-based Post-Quantum Cryptography Codes for High-Level Synthesis

Andres Upegui, Francesco Regazzoni, Andrea Guerrieri

High-level synthesis is a mature Electronics Design Automation (EDA) technology for building hardware design in a short time. It produces automatically HDL code for FPGAs out of C/C++, bridging the gap from algorithm to hardware. Nevertheless, sometimes th ...

IEEE2022