Publication

Downscaling and Short Channel Effects in Twin Gate Junctionless Vertical Slit FETs

Publications associées (32)

Negative Capacitance as Universal Digital and Analog Performance Booster for Complementary MOS Transistors

Christian Enz, Igor Stolichnov, Mihai Adrian Ionescu, Farzan Jazaeri, Ali Saeidi

Boltzmann electron energy distribution poses a fundamental limit to lowering the energy dissipation of conventional MOS devices, a minimum increase of the gate voltage, i.e. 60 mV, is required for a 10-fold increase in drain-to-source current at 300 K. Neg ...

Nature Research2019

High-performance nanowire-based E-mode Power GaN MOSHEMTs

Elison de Nazareth Matioli, Jun Ma, Minghua Zhu, Luca Nela

In this work, we demonstrate high-performance Enhancement-mode (E-mode) GaN Metal-Oxide-Semiconductor High Electron Mobility Transistors (MOS-HEMTs) on Si substrate achieved by a nanostructured gate region in combination with a large work-function gate met ...

IEEE2019

Sub-Thermionic Scalable III-V Tunnel Field-Effect Transistors Integrated on Si (100)

Mihai Adrian Ionescu, Kirsten Emilie Moselund

We present scalable III-V heterojunction tunnel FETs fabricated using a Si CMOS-compatible FinFET process flow and integrated on Si (100) substrates. The tunneling junction is fabricated through self-aligned selective p(+) GaAsSb raised source epitaxial re ...

IEEE2019

Gate Leakage Tunneling Impact on the InAs/GaSb Heterojunction Electron-Hole Bilayer Tunneling Field-Effect Transistor

Mihai Adrian Ionescu, José Luis Padilla de la Torre

Among the different types of bilayer tunneling field-effect transistors exploiting interband tunneling phenomena with tunneling directions aligned with gate-induced electric fields, the utilization of InAs/GaSb channels proves to be an appealing means to e ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2018

Characterization and Modeling of Gigarad-TID-Induced Drain Leakage Current of 28-nm Bulk MOSFETs

Christian Enz, Federico Faccio, Farzan Jazaeri, Chunmin Zhang

This paper characterizes and models the effects of total ionizing dose (TID) up to 1 Grad(SiO2) on the drain leakage current of nMOSFETs fabricated with a commercial 28-nm bulk CMOS process. Experimental comparisons among individual nMOSFETs of various siz ...

2018

Semiconductor devices with multiple channels and three-dimensional electrodes

Elison de Nazareth Matioli, Jun Ma

The present invention relates, for example, to a semiconductor structure containing multiple parallel channels in which several parallel conductive channels are formed within the semiconductor structure. Electric contact or electrostatic control over all t ...

2018

Yttrium zinc tin oxide high voltage thin film transistors

Herbert Shea, Danick Briand, Alexis Pierre Henri Marette

We demonstrate that doping the semiconductor zinc tin oxide (ZTO) with yttrium leads to a high-voltage thin film transistor (HVTFT) with enhanced switching performance. Adding 5% yttrium leads to an increase in the on-off ratio from 40 to 1000 at an operat ...

AIP American Institute of Physics2018

Polarity Control of Top Gated Black Phosphorous FETs by Workfunction Engineering of Pre-Patterned Au and Ag Embedded Electrodes

Igor Stolichnov, Mihai Adrian Ionescu, Wolfgang Amadeus Vitale, Emanuele Andrea Casu, Nicolò Oliva

We propose and experimentally demonstrate top-gated complementary n- and p-type black phosphorous field effect devices (FETs) by engineering the workfunction of pre-patterned electrodes embedded in a SiO2 bottom layer. Pre-patterned electrodes offer the ad ...

2018

Characterization of GigaRad Total Ionizing Dose and Annealing Effects on 28-nm Bulk MOSFETs

Christian Enz, Claudio Bruschini, Federico Faccio, Farzan Jazaeri, Chunmin Zhang, Alessandro Pezzotta

This paper investigates the radiation tolerance of 28-nm bulk n and pMOSFETs up to 1 Grad of total ionizing dose (TID). The radiation effects on this commercial 28-nm bulk CMOS process demonstrate a strong geometry dependence as a result of the complex int ...

2017

Modeling and optimization of Tunnel-FET architectures exploiting carrier gas dimensionality

Cem Alper

The semiconductor industry, governed by the Moore's law, has achieved the almost unbelievable feat of exponentially increasing performance while lowering the costs for years. The main enabler for this achievement has been the scaling of the CMOS transistor ...

EPFL2017

A Steep-Slope Transistor Combining Phase-Change and Band-to-Band-Tunneling to Achieve a sub-Unity Body Factor

Mihai Adrian Ionescu, Josef Andreas Schuler, Wolfgang Amadeus Vitale, Arnab Biswas, Cem Alper, Emanuele Andrea Casu, Teodor Rosca, Anna Krammer, Qun Zhao

Steep-slope transistors allow to scale down the supply voltage and the energy per computed bit of information as compared to conventional field-effect transistors (FETs), due to their sub-60 mV/decade subthreshold swing at room temperature. Currently pursu ...

Nature Research2017

GigaRad total ionizing dose and post-irradiation effects on 28 nm bulk MOSFETs

Christian Enz, Claudio Bruschini, Federico Faccio, Farzan Jazaeri, Chunmin Zhang, Alessandro Pezzotta

The DC performance of both n- and pMOSFETs fabricated in a commercial-grade 28 nm bulk CMOS process has been studied up to 1 Grad of total ionizing dose and at post-irradiation annealing. The aim is to assess the potential use of such an advanced CMOS tech ...

IEEE2016