Publications associées à A 15.8 pJ/bit/iter quasi-cyclic LDPC decoder for IEEE 802.11n in 90 nm CMOS

Publications associées (31)

A Generalized Adjusted Min-Sum Decoder for 5G LDPC Codes: Algorithm and Implementation

Andreas Peter Burg, Alexios Konstantinos Balatsoukas Stimming, Yifei Shen, Yuqing Ren, Hassan Harb

5G New Radio (NR) has stringent demands on both performance and complexity for the design of low-density parity-check (LDPC) decoding algorithms and corresponding VLSI implementations. Furthermore, decoders must fully support the wide range of all 5G NR bl ...

Ieee-Inst Electrical Electronics Engineers Inc2024

High-Throughput and Flexible Belief Propagation List Decoder for Polar Codes

Andreas Peter Burg, Alexios Konstantinos Balatsoukas Stimming, Yifei Shen, Yuqing Ren, Andreas Toftegaard Kristensen, Leyu Zhang

Due to its high parallelism, belief propagation (BP)decoding is amenable to high-throughput applications and thusrepresents a promising solution for the ultra-high peak datarate required by future communication systems. To bridge theperformance gap compare ...

Ieee-Inst Electrical Electronics Engineers Inc2024

Contemporary Logic Synthesis: with an Application to AQFP Circuit Optimization

Siang-Yun Lee

Electronic devices play an irreplaceable role in our lives. With the tightening time to market, exploding demand for computing power, and continuous desire for smaller, faster, less energy-consuming, and lower-cost chips, computer-aided design for electron ...

EPFL2024

On Speed and Advantage : Results in Information Velocity and Monitoring Problems

Reka Inovan

Information theory has allowed us to determine the fundamental limit of various communication and algorithmic problems, e.g., the channel coding problem, the compression problem, and the hypothesis testing problem. In this work, we revisit the assumptions ...

EPFL2024

Low Power LDPC Decoding by Reliable Voltage Down-Scaling

Andreas Peter Burg

Low-Density Parity-Check (LDPC) decoder is among the power hungry building blocks of wireless communication systems. Voltage scaling down to Near-Threshold (NT) voltages substantially improves energy efficiency, in theory up 10x. However, tuning the voltag ...

IEEE2023

Ultra-Low Power Short-Range 60-GHz FMCW Radar Front-End

Sammy Cerida Rengifo

The millimeter wave (mmWave) frequency band is becoming very interesting over the past years because it provides the opportunity to operate using large bandwidths which are not available at lower frequencies. This enables new communication standards suppor ...

EPFL2023

Analysis of the influence of errors in DNA-based image coding

Touradj Ebrahimi, Michela Testolina, Davi Nachtigall Lazzarotto

In the last decade, DNA has been increasingly investigated as an alternative medium for cold data storage, presenting several advantages over standard hard drives such as a higher density, longer lifespan and lower energy consumption. However, such coding ...

2023

Exploring brain-inspired multi-core heterogeneous hardware templates for low-power biomedical embedded systems

Benoît Walter Denkinger

The miniaturization of integrated circuits (ICs) and their higher performance and energy efficiency, combined with new machine learning algorithms and applications, have paved the way to intelligent, interconnected edge devices. In the medical domain, they ...

EPFL2023

An Error-Based Approximation Sensing Circuit for Event-Triggered Low-Power Wearable Sensors

David Atienza Alonso, Alexandre Sébastien Julien Levisse, Tomas Teijeiro Campo, Flavio Ponzina, Silvio Zanoli

Event-based sensors have the potential to optimize energy consumption at every stage in the signal processing pipeline, including data acquisition, transmission, processing, and storage. However, almost all state-of-the-art systems are still built upon th ...

2023

Acceleration of Control Intensive Applications on Coarse-Grained Reconfigurable Arrays for Embedded Systems

David Atienza Alonso, Miguel Peon Quiros, Benoît Walter Denkinger

Embedded systems confront two opposite goals: low-power operation and high performance. The current trend to reach these goals is toward heterogeneous platforms, including multi-core architectures with heterogeneous cores and hardware accelerators. The lat ...

2023

Individual and combined benefits of different nonequilibrium proofreading mechanisms

Paolo De Los Rios, Daniel Maria Busiello, Stefano Zamuner, Adélaïde Alice Mohr

Genome duplication, transcription, and translation are among many crucial cellular processes that need to be performed with high fidelity. However, those extremely low error rates cannot be explained with simple equilibrium thermodynamic considerations. Th ...

Amer Physical Soc2023

An Iterative Method for Mapping-Aware Frequency Regulation in Dataflow Circuits

Andrea Guerrieri, Lana Josipovic

Dataflow circuits promise to overcome the scheduling limitations of standard HLS solutions. However, their performance suffers due to timing overheads caused by their handshake communication protocol. Current pipelining solutions fail to account for logic ...

IEEE2023

Localizing Traffic Differentiation

Aikaterini Argyraki, Pavlos Nikolopoulos, Muhammad Abdullah, Zeinab Shmeis

Network neutrality is important for users, content providers, policymakers, and regulators interested in understanding how network providers differentiate performance. When determining whether a network differentiates against certain traffic, it is importa ...

2023

Relaxed Locally Correctable Codes With Nearly-Linear Block Length And Constant Query Complexity

Alessandro Chiesa

Locally correctable codes (LCCs) are error correcting codes C : \Sigmak \rightarrow \Sigman which admit local algorithms that correct any individual symbol of a corrupted codeword via a minuscule number of queries. For systematic codes, this notion is stro ...

SIAM PUBLICATIONS2022

Symmetry in design and decoding of polar-like codes

Kirill Ivanov

The beginning of 21st century provided us with many answers about how to reach the channel capacity. Polarization and spatial coupling are two techniques for achieving the capacity of binary memoryless symmetric channels under low-complexity decoding algor ...

EPFL2022

Ultra-High-Throughput EMS NB-LDPC Decoder with Full-Parallel Node Processing

Hassan Harb

This paper presents an ultra-high-throughput decoder architecture for NB-LDPC codes based on the Hybrid Extended Min-Sum algorithm. We introduce a new processing block that updates a check node and its associated variable nodes in a fully pipelined way, th ...

SPRINGER2022

List Ordered Statistics Decoders for Polar Codes

Andreas Peter Burg, Yifei Shen, Leyu Zhang

The de-facto standard decoding algorithm for polar codes, successive cancellation list (SCL) decoding, is a breadth-first search algorithm. By keeping a list of candidate codewords, SCL decoding improves the performance as the list size L increases. Howeve ...

IEEE2022

Fast Sequence Repetition Node-Based Successive Cancellation List Decoding for Polar Codes

Andreas Peter Burg, Alexios Konstantinos Balatsoukas Stimming, Yifei Shen, Yuqing Ren, Andreas Toftegaard Kristensen

Compared with the bit-wise successive cancellation list (SCL) decoding of polar codes, the node-based Fast SCL decoding significantly reduces the decoding latency by identifying special constituent codes and decoding these in parallel. To further reduce th ...

IEEE2022

Secret Key Generation Using Short Blocklength Polar Coding Over Wireless Channels

Yanina Yurina Shkel

This paper investigates the problem of secret key generation from correlated Gaussian random variables in the short blocklength regime. Short blocklengths are commonly employed in massively connected IoT sensor networks in 5G and beyond wireless systems. P ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2022

An All-Digital 1 Mbps, 57 pJ/bit Bluetooth Low Energy (BLE) Backscatter ASIC in 65 nm CMOS

James Daniel Rosenthal

We present an all-digital application specific integrated circuit (ASIC) that implements Bluetooth Low Energy (BLE)-compatible backscatter communication. The ASIC was fabricated in a 65 nm CMOS process and occupies an active area of 0.12 mm(2) while consum ...

IEEE2022