Publication

A 17 ps Resolution, Temperature Compensated Time-to-Digital Converter in FPGA Technology

Publications associées (32)

Miss-Optimized Memory Systems: Turning Thousands of Outstanding Misses into Reuse Opportunities

Even if Dennard scaling came to an end fifteen years ago, Moore' s law kept fueling an exponential growth in compute performance through increased parallelization. However, the performance of memory and, in particular, Dynamic Random Access Memory (DRAM), ...

EPFL2021

Beyond Cameras: Real-Time High-Resolution 3D and Panoramic MultiView Vision Systems with Their Applications

Bilal Demir

The cameras are invented by imitating the human visual system to capture the scene. The camera technologies have been substantially advanced in recent years. 108 MP resolution with 100x hybrid zoom has become standard features for smartphone flagships. In ...

EPFL2020

Timing-Driven Placement for FPGA Architectures with Dedicated Routing Paths

Paolo Ienne, Grace Zgheib, Stefan Nikolic

The idea of introducing dedicated, fast paths between certain FPGA elements in order to reduce delay is neither new nor particularly hard to come up with. What is less obvious, however, is how to put such paths to actual use. In this work, we propose an ef ...

IEEE2020

Are Cloud FPGAs Really Vulnerable to Power Analysis Attacks?

Francesco Regazzoni, Mirjana Stojilovic, Louis Coulon, Ognjen Glamocanin

Recent works have demonstrated the possibility of extracting secrets from a cryptographic core running on an FPGA by means of remote power analysis attacks. To mount these attacks, an adversary implements a voltage fluctuation sensor in the FPGA logic, rec ...

IEEE2020

Snap-On User-Space Manager for Dynamically Reconfigurable System-on-Chips

Paolo Ienne, Sahand Kashani, Andrea Guerrieri

Due to increased embedded processing requirements, modern SoCs are becoming heterogeneous computing platforms by combining traditional processing units with custom reconfigurable hardware accelerators (HAs) on an FPGA fabric. However, efficiently managing ...

2019

FPGA-Assisted Deterministic Routing for FPGAs

Mirjana Stojilovic, Dario Korolija

FPGA routing is one of the most time-consuming steps of FPGA compilation, often preventing fast edit-compile-test cycles in prototyping and development. There have been attempts to accelerate FPGA routing using algorithmic improvements, multi-core or multi ...

2019

High Speed SAR ADC Architectures in 28nm FDSOI CMOS

Mustafa Kilic

The demand on high speed Analog to Digital Converters (ADCs) has increased considerably the last years. From communications circuit to high speed oscilloscopes, Giga Samples per second (GS/s) ADCs are requested. With the scaling of the CMOS technology, des ...

EPFL2019

Low-Power Design of Digital VLSI Circuits around the Point of First Failure

Andrea Bonetti

As an increase of intelligent and self-powered devices is forecasted for our future everyday life, the implementation of energy-autonomous devices that can wirelessly communicate data from sensors is crucial. Even though techniques such as voltage scaling ...

EPFL2019

DynaBurst: Dynamically Assemblying DRAM Bursts over a Multitude of Random Accesses

Paolo Ienne, Mikhail Asiatici

The effective bandwidth of the FPGA external memory, usually DRAM, is extremely sensitive to the access pattern. Nonblocking caches that handle thousands of outstanding misses (miss-optimized memory systems) can dynamically improve bandwidth utilization wh ...

IEEE2019

A machine learning approach for power gating the FPGA routing network

Mirjana Stojilovic, Hossein Asadi

Power gating is a common approach for reducing circuit static power consumption. In FPGAs, resources that dominate static power consumption lie in the routing network. Researchers have proposed several heuristics for clustering multiplexers in the routing ...

IEEE COMPUTER SOC2019

A 6.5-GHz Cryogenic All-Pass Filter Circulator in 40-nm CMOS for Quantum Computing Applications

Edoardo Charbon, Fabio Sebastiano, Andrea Ruffino, Yatao Peng

Cryogenic solid-state quantum processors require classical control and readout electronics; to achieve compactness and scalability, cryogenic integrated circuits have been recently proposed for this goal. Circulators are widely used in readout circuits, ho ...

2019

Post-P&R Performance and Power Analysis for RRAM-based FPGAs

Giovanni De Micheli, Xifan Tang, Pierre-Emmanuel Julien Marc Gaillardon, Edouard Giacomin

Resistive Random Access Memory (RRAM)-based FPGAs are predicted to outperform conventional FPGAs architectures in area, delay and power over a wide range of voltage operations, allowing novel energy-quality trade-offs for reconfigurable computing. The oppo ...

2018