Tunnel FET with non-uniform gate capacitance for improved device and circuit level performance

Mihai Adrian Ionescu, Luca De Michielis, Cem Alper, Livio Lattanzio, Nilay Dagtekin
2012
Conference Papers

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Mihai Adrian Ionescu, Luca De Michielis, Cem Alper, Livio Lattanzio, Nilay Dagtekin
2012
Conference Papers

Source officielle

Publications associées (11)

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https://infoscience.epfl.ch/entities/publication/69abb1df-8e65-4817-b30c-33c25ee30b75

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Publications associées (11)

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Fully integrated Si:HfO2 Negative Capacitance 2D-2D WSe2/SnSe2 Subthermionic Tunnel FETs

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We report the first experimental demonstration and performance characterization of a fully integrated negative capacitance (NC) WSe2/SnSe2 p-type Tunnel FETs (TFETs), validating the use of NC as a technology booster to achieve a significantly improved sub- ...

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This paper presents an in-depth DC characterization of a 22 nm FDSOI CMOS technology down to deep cryogenic temperature, i.e., 2.95 K. The impact of the back-gate voltage (V-back) on device performance, i.e., threshold voltage (V-T) and carrier transport, ...

PERGAMON-ELSEVIER SCIENCE LTD2022

Deep-UV-Enhanced Approach for Low-Temperature Solution Processing of IZO Transistors with High-k AlOx/YAlOx Dielectric

Danick Briand, Jaemin Kim, Alessio Mancinelli

Solution processing is an attractive alternative to standard vacuum fabrication techniques for the large-area manufacturing of metal oxide (MOx)-based electron devices. Here, we report on thin-film transistors (TFTs) based on a solution-processed indium zi ...

AMER CHEMICAL SOC2020