Doping Engineering for PDP Optimization in SPADs Implemented in 55-nm BCD Process

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In this article, we present 10 mu m diameter SPADs fabricated in 110 nm CIS technology based on an N (+) /HVPW junction, with enhanced sensitivity at short wavelengths. To reduce tunneling noise due to the highly-doped layers in the process, a doping compe ...

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This paper presents a single-photon avalanche diode (SPAD) in 55 nm bipolar-CMOSDMOS (BCD) technology. In order to realize a SPAD having sub-20 V breakdown voltage for mobile applications while preventing high tunneling noise, a high-voltage N-well availab ...

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A time-resolved multi-gate ion sensitive field effect transducer, including a silicon layer, a P-doped region in the silicon layer and a first electrode in electric connection with the P doped region, a N-doped region in the silicon layer and a second elec ...

Doping Engineering for PDP Optimization in SPADs Implemented in 55-nm BCD Process

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