Publications associées à Physically clustered Forward Body Biasing for variability compensation in nanometer CMOS design

Publications associées (37)

The Development of Embedded Computing as a Discipline [special Section on 2025 Ieee Kirchhoff Award]

To mark the occasion of festschrift of Prof. Giovanni De Micheli, this paper takes a retrospective look at research though the lines pursued by Prof. De Micheli that led to the emergence of Embedded Systems as an enduring discipline. In telling this narrat ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2025

Contemporary Logic Synthesis: with an Application to AQFP Circuit Optimization

Siang-Yun Lee

Electronic devices play an irreplaceable role in our lives. With the tightening time to market, exploding demand for computing power, and continuous desire for smaller, faster, less energy-consuming, and lower-cost chips, computer-aided design for electron ...

EPFL2024

Emulating Multimemristive Behavior of Silicon Nanowire-Based Biosensors by Using CMOS-Based Implementations

Kapil Bhardwaj, Sandro Carrara, Junrui Chen

The research presented in this article draws inspiration from previous efforts aimed at replicating the functions of various solid-state memristors using a variety of materials. The memristor circuit emulator serves as a cost-effective tool for circuit des ...

Ieee-Inst Electrical Electronics Engineers Inc2024

A 500 x 500 Dual-Gate SPAD Imager With 100% Temporal Aperture and 1 ns Minimum Gate Length for FLIM and Phasor Imaging Applications

Edoardo Charbon, Claudio Bruschini, Arin Can Ülkü, Andrei Ardelean, Paul Mos, Michael Alan Wayne

In this article, we report on SwissSPAD3 (SS3), a 500 x 500 pixel single-photon avalanche diode (SPAD) array, fabricated in 0.18-mu m CMOS technology. In this sensor, we introduce a novel dual-gate architecture with two contiguous temporal windows, or gate ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2022

Shrinking FPGA Static Power via Machine Learning-Based Power Gating and Enhanced Routing

Mirjana Stojilovic

Despite FPGAs rapidly evolving to support the requirements of the most demanding emerging applications, their high static power consumption, concentrated within the routing resources, still presents a major hurdle for low-power applications. Augmenting the ...

2021

Synthesizing General-Purpose Code Into Dynamically Scheduled Circuits

Paolo Ienne, Andrea Guerrieri, Lana Josipovic

Since their inception more than thirty years ago, field-programmable gate arrays (FPGAs) have been widely used to implement a myriad of applications from different domains. As a result of their low-level hardware reconfigurability, FPGAs have much faster d ...

2021

A Visionary Look at the Security of Reconfigurable Cloud Computing

Francesco Regazzoni, Mirjana Stojilovic

Field-programmable gate arrays (FPGAs) have become critical components in many cloud computing platforms. These devices possess the fine-grained parallelism and specialization needed to accelerate applications ranging from machine learning to networking an ...

2023

Towards Deeply Scaled 3D MPSoCs with Integrated Flow Cell Array Technology

David Atienza Alonso, Marina Zapater Sancho, Alexandre Sébastien Julien Levisse, Mohamed Mostafa Sabry Aly, Halima Najibi

Deeply-scaled three-dimensional (3D) Multi-Processor Systems-on-Chip (MPSoCs) enable high performance and massive communication bandwidth for next-generation computing. However, as process nodes shrink, temperature-dependent leakage dramatically increases, ...

2020

Energy-Efficient Electronic Functions Based on the Co-integration of 2D and Ferroelectric Materials

Sadegh Kamaei Bahmaei

The digital revolution has significantly transformed our world over the past decades, driven by the scaling of transistor dimensions and the exponential increase in computation power. However, as the CMOS scaling era approaches its end, the semiconductor i ...

EPFL2023

Analysis of Functional Errors Produced by Long-Term Workload-Dependent BTI Degradation in Ultra-Low Power Processors

David Atienza Alonso, Alexandre Sébastien Julien Levisse, Miguel Peon Quiros, Ruben Braojos Lopez, Loris Gérard Duch

Aging effects in digital circuits change the switching characteristics of their transistors, resulting in timing violations that can lead to functional errors at the system level. In particular, BTI is a degradation effect that changes the threshold voltag ...

2020

Importance of Ground Return Parameters in Transient Analysis of Overhead Wires

Farhad Rachidi-Haeri, Rafael Silva Alipio, Naiara Figueiredo Duarte

This study assesses the accuracy of the formulations of Carson and Sunde in modeling ground effects on overhead wires, particularly for high-frequency transients and high-resistivity soils. The results reveal that these traditional formulations tend to und ...

International Union of Radio Science (URSI)2023

Silicon Nitride Integrated Nonlinear Photonics

Junqiu Liu

Recently, microresonator-based dissipative Kerr soliton frequency combs ( "soliton microcomb " ) have emerged as miniaturized optical frequency combs. So far, soliton microcombs have been realized in many CMOS-compatible material platforms including silico ...

EPFL2020

Evaluating, Exploiting, and Hiding Power Side-Channel Leakage of Remote FPGAs

Ognjen Glamocanin

The pervasive adoption of field-programmable gate arrays (FPGAs) in both cyber-physical systems and the cloud has raised many security issues. Being integrated circuits, FPGAs are susceptible to fault and power side-channel attacks, which require physical ...

EPFL2023

A Low-Power 9-Bit 222 MS/s Asynchronous SAR ADC in 65 nm CMOS

Yusuf Leblebici, Firat Çelik, Ayça Akkaya

This paper presents a 9-bit 222 MS/s low-power asynchronous single-bit/cycle successive approximation register (SAR) ADC. The SAR ADC combines techniques such as asynchronous clocking, binary-weighted custom-designed capacitive DAC with small unit capacito ...

IEEE2020

A Delay and Power Efficient Voltage Level Shifter with Low Leakage Power

Alexandre Schmid, Mehdi Saberi

This paper presents a new power-efficient and high-speed voltage level shifter. In the proposed structure, the existing contentions at the internal nodes are reduced using auxiliary transistors and feedback networks, leading to a significant reduction in t ...

IEEE2023

At the end of scaling: 2D materials for computing and sensing applications

Nicolò Oliva

In the past half-century, the digital revolution completely changed the world we live in and the ways we experience it. Over this period, the underlying force supporting the continuous technological development has been the geometrical scaling of transisto ...

EPFL2020

Subthreshold Mismatch in Nanometer CMOS at Cryogenic Temperatures

Edoardo Charbon

Cryogenic device models are essential for the reliable design of the cryo-CMOS electronic interface necessary to build future large-scale quantum computers. This paper reports the characterization of the drain-current mismatch of NMOS and PMOS devices fabr ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2020

High Input Impedance Front-End Amplifier for Noncontact Bio-Potential Recording

Alexandre Schmid

In this paper, a high input impedance front-end amplifier is proposed for non-contact bio-potential recording systems. The proposed structure uses a positive feedback network to deliver a neutralization current back to the input node of the circuit to neut ...

Institute of Electrical and Electronics Engineers Inc.2023

Optimal sizing and siting of energy storage systems considering curtailable photovoltaic generation in power distribution networks

Fabrizio Sossan, Rahul Kumar Gupta

This work proposes a method for optimal planning (sizing and siting) energy storage systems (ESSs) in power distribution grids while considering the option of curtailing photo-voltaic (PV) generation. More specifically, for a given PV generation capacity t ...

2023

A machine learning approach for power gating the FPGA routing network

Mirjana Stojilovic

Power gating is a common approach for reducing circuit static power consumption. In FPGAs, resources that dominate static power consumption lie in the routing network. Researchers have proposed several heuristics for clustering multiplexers in the routing ...

IEEE COMPUTER SOC2019