Publications associées à JESD204B Compliant 12.5 Gb/s LVDS and SST Transmitters in 28 nm FD-SOI CMOS

Graph generative deep learning models with an application to circuit topologies

Modern integrated circuits are tiny yet incredibly complex technological artifacts, composed of millions and billions of individual structures working in unison. Managing their complexity and facilitating their design drove part of the co-evolution of mode ...

EPFL2024

In Liquido Computation with Electrochemical Transistors and Mixed Conductors for Intelligent Bioelectronics

Eleni Stavrinidou, Matteo Cucchi

Next-generation implantable computational devices require long-term-stable electronic components capable of operating in, and interacting with, electrolytic surroundings without being damaged. Organic electrochemical transistors (OECTs) emerged as fitting ...

Wiley-V C H Verlag Gmbh2023

Miniaturised, Wireless and Distributed Neural Interface Toward Cortical Visual Prosthesis

Gian Luca Barbruni

Over the last decades, implantable neural interfaces have been extensively explored and effectively deployed to address neurological and mental health disorders. The existing solutions present several limitations. Firstly, the physical size of the implanta ...

EPFL2023

An Error-Based Approximation Sensing Circuit for Event-Triggered Low-Power Wearable Sensors

David Atienza Alonso, Silvio Zanoli, Alexandre Sébastien Julien Levisse, Tomas Teijeiro Campo, Flavio Ponzina

Event-based sensors have the potential to optimize energy consumption at every stage in the signal processing pipeline, including data acquisition, transmission, processing, and storage. However, almost all state-of-the-art systems are still built upon th ...

2023

An All-Digital 1 Mbps, 57 pJ/bit Bluetooth Low Energy (BLE) Backscatter ASIC in 65 nm CMOS

James Daniel Rosenthal

We present an all-digital application specific integrated circuit (ASIC) that implements Bluetooth Low Energy (BLE)-compatible backscatter communication. The ASIC was fabricated in a 65 nm CMOS process and occupies an active area of 0.12 mm(2) while consum ...

IEEE2022

Energy-Efficient Design Techniques for High-Speed Wireline Serial Links

Firat Çelik

The exponential growth in computing power and multimedia services has caused a tremendous increase in data traffic in recent years. This increase in data traffic brings a strong demand for data bandwidth of electrical input/output (I/O) links and pushes th ...

EPFL2021

Resource Trade-Offs in Circuits and Systems: from Neurotechnology to Communications

Arda Uran

This thesis aims to explore and exploit trade-offs in integrated circuits and systems to overcome the fundamental bottlenecks faced by future data acquisition and communication systems. Specifically, we target the emerging implantable neurotechnology and t ...

EPFL2021

Nonreciprocity in Bianisotropic Systems with Uniform Time Modulation

Xiaoqiang Wang, Mohammad Sajjad Mirmoosa, Xiao Wang

Physical systems with material properties modulated in time provide versatile routes for designing magnetless nonreciprocal devices. Traditionally, nonreciprocity in such systems is achieved exploiting both temporal and spatial modulations, which inevitabl ...

AMER PHYSICAL SOC2020

A 161-mW 56-Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14-nm FinFET

Yusuf Leblebici, Alessandro Cevrero, Andreas Peter Burg, Gain Kim, Lukas Kull, Thomas Toifl, Cosimo Aprile, Ilter Ozkaya

This article introduces a wireline receiver (RX) data-path employing discrete multi-tone (DMT) modulation for communicating over electrical links. The DMT RX incorporates a fully digital equalization data-path, with a synthesized and automatically placed a ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2020

A Logic Synthesis Toolbox for Reducing the Multiplicative Complexity in Logic Networks

Giovanni De Micheli, Luca Gaetano Amarù, Eleonora Testa, Mathias Soeken, Heinz Riener

Logic synthesis is a fundamental step in the realization of modern integrated circuits. It has traditionally been employed for the optimization of CMOS-based designs, as well as for emerging technologies and quantum computing. Recently, it found applicatio ...

IEEE2020

Wireless Power Transfer and Data Communication for Implantable Autonomous Monitoring and Detection of Epilepsy In Vivo

Kerim Türe

The impact of technological advancement became significant and still has an essential role to play in the diagnosis and treatment of diseases. Nowadays, personalized medicine and therapy are on the rise as a consequence of the developed and cheaper medical ...

EPFL2019

ISI Sensitivity of PAM Signaling for Very High-Speed Short-Reach Copper Links

Yusuf Leblebici, Seyed Armin Tajalli, Ayça Akkaya, Firat Çelik

This paper presents a comparative study, analyzing the potentials of pulse amplitude modulation (PAM) for implementing next generation high-speed copper wireline links. This comparative study analyzes the sensitivities of PAM2, PAM4 and PAM8 to inter-symbo ...

IEEE2019

Design Considerations and Performance Trade-Offs for 56Gb/s Discrete Multi-Tone Electrical Link

Yusuf Leblebici, Gain Kim, Thomas Toifl

For communicating over mid-to-long-reach electrical links at a data-rate above 56Gb/s, ADC-based receiver (RX) has become a dominant architecture due to its strong equalization capability using complex digital signal processing algorithm benefiting from th ...

IEEE2019

Adaptive Receiver Design for High Speed Optical Communication

Ilter Ozkaya

Conventional input/output (IO) links consume power, independent of changes in the bandwidth demand by the system they are deployed in. As the system is designed to satisfy the peak bandwidth demand, most of the time the IO links are idle but still consumin ...

EPFL2018

Satisfiability-Based Methods for Digital Circuit Design, Debug, and Optimization

Andrew James Becker

Designing digital circuits well is notoriously difficult. This difficulty stems in part from the very many degrees of freedom inherent in circuit design, typically coupled with the need to satisfy various constraints. In this thesis, we demonstrate how for ...

EPFL2018

FPGA-SPICE: A Simulation-Based Architecture Evaluation Framework for FPGAs

Giovanni De Micheli, Xifan Tang, Pierre-Emmanuel Julien Marc Gaillardon, Edouard Giacomin

In this paper, we developed a simulation-based architecture evaluation framework for field-programmable gate arrays (FPGAs), called FPGA-SPICE, which enables automatic layout-level estimation and electrical simulations of FPGA architectures. FPGA-SPICE can ...

2018

A Timing-Monitoring Sequential for Forward and Backward Error-Detection in 28 nm FD-SOI

Andreas Peter Burg, Jeremy Hugues-Felix Constantin, Andrea Bonetti, Adam Shmuel Teman

The increasing impact of variability on near-threshold nanometer circuits calls for a tighter online monitoring and control of the available timing margins. Error-detection sequentials are widely used together with error-correction techniques to operate di ...

IEEE2018

Parallel Implementation Technique of Digital Equalizer for Ultra-High-Speed Wireline Receiver

Yusuf Leblebici, Alessandro Cevrero, Gain Kim, Lukas Kull, Thomas Toifl, Cosimo Aprile, Ilter Ozkaya

This paper presents a parallel implementation technique of digital equalizer for high-speed wireline serial link receiver (RX). In wireline RX, inter-symbol interference (ISI) is mitigated by continuous-time linear equalizer, and the remaining ISI is cance ...

2018

Multi-Tone Signaling and ADC-Based Digital Receiver for High-Speed Wireline Serial Links

Gain Kim

The exponential growth of Internet traffic and related demands for higher communication speed pushes processor-to-processor and processor-to-memory interconnects to provide further higher data-rate. Often time, processor-to-memory interconnectsâ speed is ...

EPFL2018

A Sub-μW/Channel, 16-Channel Seizure Detection and Signal Acquisition SoC Based on Multichannel Compressive Sensing

Alexandre Schmid, Reza Ranjandish

An accurate 16-channel seizure detection system-on-chip is presented, which is based on extracting features from the compressed recorded data using multichannel compressive sensing (MCS). MCS is used to reduce the transmission data rate of sparse biologica ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2018