Publications associées à Manticore: Hardware-Accelerated RTL Simulation with Static Bulk-Synchronous Parallelism

Publications associées (7)

Highly Parallel RTL Simulation

Verification and testing of hardware heavily relies on cycle-accurate simulation of RTL. As single-processor performance is growing only slowly, conventional, single-threaded RTL simulation is becoming impractical for increasingly complex chip designs and ...

EPFL2024

Startup Analysis and Design of Self-Powered Auxiliary Power Supply in Input-Series System With Small Submodule Capacitance

Rui Wang

For filling higher input voltage requirement, the input-series system based on attainable power devices is prevalent in industry. Specifically, its auxiliary power supply (APS) is self-powered from submodule (SM) capacitance on medium/high voltage occasion ...

Ieee-Inst Electrical Electronics Engineers Inc2024

Enhancing Delay-Driven LUT Mapping with Boolean Decomposition

Giovanni De Micheli, Alessandro Tempia Calvino

Ashenhurst-Curtis decomposition (ACD) is a decomposition technique used, in particular, to map combinational logic into lookup tables (LUTs) structures when synthesizing hardware designs. However, available implementations of ACD suffer from excessive comp ...

2024

A Gradient-Gated SPAD Array for Non-Line-of-Sight Imaging

Edoardo Charbon, Francesco Gramuglia, Myung Jae Lee, Pouyan Keshavarzian, Jiuxuan Zhao

Time-resolved non-line-of-sight (NLOS) imaging based on single-photon avalanche diode (SPAD) detectors have demonstrated impressive results in recent years. To acquire adequate number of indirect photons from a hidden scene in the presence of overwhelming ...

Ieee-Inst Electrical Electronics Engineers Inc2024

An Error-Based Approximation Sensing Circuit for Event-Triggered Low-Power Wearable Sensors

David Atienza Alonso, Alexandre Sébastien Julien Levisse, Tomas Teijeiro Campo, Flavio Ponzina, Silvio Zanoli

Event-based sensors have the potential to optimize energy consumption at every stage in the signal processing pipeline, including data acquisition, transmission, processing, and storage. However, almost all state-of-the-art systems are still built upon th ...

2023

IIBLAST: Speeding Up Commercial FPGA Routing by Decoupling and Mitigating the Intra-CLB Bottleneck

Mirjana Stojilovic, Stefan Nikolic, Shashwat Shrivastava

We identified that in modern commercial FPGAs, routing signals from the general interconnect to the configurable logic blocks (CLBs) through a very sparse input interconnect block (IIB) represents a significant runtime bottleneck. This is despite academic ...

IEEE2023

The Case for Performance Interfaces for Hardware Accelerators

Jiacheng Ma, George Candea, Aikaterini Argyraki, Rishabh Ramesh Iyer

While systems designers are increasingly turning to hardware accelerators for performance gains, realizing these gains is painstaking and error-prone. It can take several person-months to determine if a given accelerator is a good fit for a given piece of ...

2023