Manticore: Hardware-Accelerated RTL Simulation with Static Bulk-Synchronous Parallelism

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Verification and testing of hardware heavily relies on cycle-accurate simulation of RTL. As single-processor performance is growing only slowly, conventional, single-threaded RTL simulation is becoming impractical for increasingly complex chip designs and ...

For filling higher input voltage requirement, the input-series system based on attainable power devices is prevalent in industry. Specifically, its auxiliary power supply (APS) is self-powered from submodule (SM) capacitance on medium/high voltage occasion ...

Ashenhurst-Curtis decomposition (ACD) is a decomposition technique used, in particular, to map combinational logic into lookup tables (LUTs) structures when synthesizing hardware designs. However, available implementations of ACD suffer from excessive comp ...

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Event-based sensors have the potential to optimize energy consumption at every stage in the signal processing pipeline, including data acquisition, transmission, processing, and storage. However, almost all state-of-the-art systems are still built upon th ...

We identified that in modern commercial FPGAs, routing signals from the general interconnect to the configurable logic blocks (CLBs) through a very sparse input interconnect block (IIB) represents a significant runtime bottleneck. This is despite academic ...

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Manticore: Hardware-Accelerated RTL Simulation with Static Bulk-Synchronous Parallelism

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Highly Parallel RTL Simulation

Startup Analysis and Design of Self-Powered Auxiliary Power Supply in Input-Series System With Small Submodule Capacitance

Enhancing Delay-Driven LUT Mapping with Boolean Decomposition

A Gradient-Gated SPAD Array for Non-Line-of-Sight Imaging

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IIBLAST: Speeding Up Commercial FPGA Routing by Decoupling and Mitigating the Intra-CLB Bottleneck

The Case for Performance Interfaces for Hardware Accelerators