The Curie temperature as a key design parameter of ferroelectric Field Effect Transistors

Interest in Ferroelectric FETs originates from their potential as non-volatile memories and, more recently, as abrupt switches. In this work, we focus on the role of the Curie temperature of the gate stack on the performance of Fe-FETs. The proposed study is based on thin film SOI Fe-FETs using organic ferroelectric gate stacks (45 nm P(VDF-TrFE) 70%-30% layer on top of 10 nm thermal SiO2). The device static characteristics are investigated from 25°C up to 155°C, from ferroelectric to paraelectric phase. We report a maximum of the transconductance at the Curie Temperature (Tc), where the ferroelectric material loses its spontaneous polarization and the transistor loses its hysteresis. The reported increase of current and transconductance with the temperature up to Tc are in contrast with the behavior in any conventional MOSFET. The experimental results are supported by an appropriate analytical model. We suggest that the Curie Temperature of the gate stack is a key design parameter for the use of Fe-FETs as non-hysteretic switches with increased on-current, close or beyond Tc, or as memory cells, in the hysteretic domain, much below Tc.