Publications associées à A DAC Assisted Speed Enhancement Technique for High Resolution SAR ADC

Publications associées (29)

Enhanced feedback performance in off-resonance AFM modes through pulse train sampling

Georg Fantner, Marcos Penedo Garcia, Santiago Harald Andany, Mustafa Kangül, Navid Asmari Saadabad

Dynamic atomic force microscopy (AFM) modes that operate at frequencies far away from the resonance frequency of the cantilever (off-resonance tapping (ORT) modes) can provide high-resolution imaging of a wide range of sample types, including biological sa ...

Beilstein-Institut2024

An Error-Based Approximation Sensing Circuit for Event-Triggered Low-Power Wearable Sensors

David Atienza Alonso, Alexandre Sébastien Julien Levisse, Tomas Teijeiro Campo, Flavio Ponzina, Silvio Zanoli

Event-based sensors have the potential to optimize energy consumption at every stage in the signal processing pipeline, including data acquisition, transmission, processing, and storage. However, almost all state-of-the-art systems are still built upon th ...

2023

Cascaded all-optical quantization employing step-size MMI and shape-optimized power splitter

Jijun He

As a key unit of future high-throughput communications, optical analog to digital converter (OADC) with all-optical quantizer element that simultaneously possesses high resolution, large bandwidth and compact size is highly promising. A pending issue of co ...

ELSEVIER SCI LTD2023

High-Speed ADC Design and Optimization for Wireline Links

Ayça Akkaya

The ever-growing global internet traffic has increased demand for higher speed data transmission. As the bandwidth requirements of wireline links increase, extensive digital equalization techniques are required to compensate for the high-frequency channel ...

EPFL2021

An 8-Bit 800 MS/s Loop-Unrolled SAR ADC With Common-Mode Adaptive Background Offset Calibration in 28 nm FDSOI

Yusuf Leblebici, Firat Çelik, Ayça Akkaya

This paper presents a low-power single-channel 8-bit loop-unrolled (LU) successive approximation register (SAR) analog-to-digital-converter (ADC) with a novel common-mode adaptive background comparator offset calibration scheme. LU-SAR ADCs use multiple co ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2021

Uncertain Sampling with Certain Priors

Golnooshsadat Elhami

Sampling has always been at the heart of signal processing providing a bridge between the analogue world and discrete representations of it, as our ability to process data in continuous space is quite limited. Furthermore, sampling plays a key part in unde ...

EPFL2021

Asynchronous sar adc with unit length capacitors and constant common mode monotonic switching

Volkan Cevher, Arda Uran

A Successive Approximation Register Analog-to-Digital Converter (SAR ADC) comprising a Track-and-Hold (T/H) switch configured for a sampling of an input voltage in the form of charge onto a capacitor; a Capacitive Digital-to- Analog Converter (CD AC) opera ...

2021

Nanowatt Acoustic Inference Sensing Exploiting Nonlinear Analog Feature Extraction

Christian Enz, Minhao Yang

Ultralow-power sensing with inference functionality embedded in sensor nodes is essential for enabling the emerging pervasive intelligence. For acoustic inference sensing, the feature extraction can take advantage of power-efficient analog circuits. Howeve ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2021

A Low-Power 9-Bit 222 MS/s Asynchronous SAR ADC in 65 nm CMOS

Yusuf Leblebici, Firat Çelik, Ayça Akkaya

This paper presents a 9-bit 222 MS/s low-power asynchronous single-bit/cycle successive approximation register (SAR) ADC. The SAR ADC combines techniques such as asynchronous clocking, binary-weighted custom-designed capacitive DAC with small unit capacito ...

IEEE2020

An Event-Based System for Low-Power ECG QRS Complex Detection

David Atienza Alonso, Tomas Teijeiro Campo, Silvio Zanoli

One of the greatest challenges in the design of modern wearable devices is energy efficiency. While data processing and communication have received a lot of attention from the industry and academia, leading to highly efficient microcontrollers and transmis ...

IEEE2020

High Speed SAR ADC Architectures in 28nm FDSOI CMOS

Mustafa Kilic

The demand on high speed Analog to Digital Converters (ADCs) has increased considerably the last years. From communications circuit to high speed oscilloscopes, Giga Samples per second (GS/s) ADCs are requested. With the scaling of the CMOS technology, des ...

EPFL2019

Supplementary Material for "Optimized Sampling Rate for Voltammetry-Based Electrochemical Sensing in Wearable and IoT Applications"

Sandro Carrara, Danilo Demarchi, Simone Aiassa

The Voltammetry-Based Sensing (VBS) methods are extremely interesting due to high specificity in several biochemical applications. Several considerations can be applied to use this method to measure different analytes, and implement efficient and optimized ...

2019

Optimized Sampling Rate for Voltammetry-Based Electrochemical Sensing in Wearable and IoT Applications

Sandro Carrara, Simone Aiassa, Danilo Demarchi

The recent advancements in electrochemical measurements are guiding the development of new platforms for in situ point-of-care monitoring of human-metabolite, markers, and drugs. Despite this, the application of voltammetry-based sensing (VBS) techniques i ...

2019

Analysis of photosensor frontends for biomedical applications: a focus on noise

Paul Stanislas Gosselin

Photosensing has proven to be highly useful in biomedical research and medical care. Being able to detect and quantify the light emitted by fluorescent or bioluminescent reporters has significantly participated in the development of new cancer treatments a ...

EPFL2019

A Learning-Based Framework for Quantized Compressed Sensing

Volkan Cevher, Rabeeh Karimi Mahabadi, Junhong Lin

Sparse recovery from undersampled random quan- tization measurements is a recent active research topic. Previous work asserts that stable recovery can be guaranteed via the basis pursuit dequantizer (BPDQ) if the measurements number is large enough, consid ...

IEEE Institute of Electrical and Electronics Engineers2019

Reconfigurable optical generation of nine Nyquist WDM channels with sinc-shaped temporal pulse trains using a single microresonator-based Kerr frequency comb

Tobias Kippenberg, Maxim Karpov, Martin Hubert Peter Pfeiffer, Arne Kordts, Fatemeh Alishahi

Sinc-shaped temporal pulse trains have a spectrally efficient, rectangular Nyquist spectrum. We demonstrate the simultaneous and reconfigurable optical generation of multiple Nyquist-shaped wavelength-division-multiplexed (WDM) channels having temporal sin ...

OPTICAL SOC AMER2019

Nonlinear piezoelectric vibration energy harvester with frequency-tuned impacting resonators for improving broadband performance at low frequencies

Nico de Rooij, Danick Briand, Andres Felipe Vasquez Quintero, Robert Andrew Lockhart

The paper reports on a nonlinear frequency up-converting vibration energy harvester with enhanced broadband performance below 50 Hz, which is attained by leveraging vibro-impact interaction between two high-frequency piezoelectric generators and two low-fr ...

IOP PUBLISHING LTD2019

Tokamak plasma edge studies by microwave short-pulse reflectometry and backscattering

Pedro Andres Molina Cabrera

Moving towards an increased understanding of the dynamic processes in the edge of tokamak plasmas requires continuous innovation in diagnostic capabilities, pushing the envelope in both spatial and temporal dimenstions. Plasma density and rotation, and the ...

EPFL2019

A 10b SAR ADC with Widely Scalable Sampling Rate and AGC Amplifier Front-End

Yusuf Leblebici, Seyed Armin Tajalli, Firat Çelik, Ayça Akkaya

This paper presents a low power successive approximation register (SAR) ADC and its front-end automatic gain control (AGC) amplifier designed in 65nm CMOS technology. Digitally controlled variable gain amplifier (VGA) in AGC loop is used to maximize the dy ...

IEEE2018

A Pipelined Speed Enhancement Technique for CDAC-Threshold Configuring SAR ADC

Yusuf Leblebici, Mustafa Kilic

In this paper, a novel SAR ADC architecture enabling very high speed operation is presented. Based on a hybrid capacitive DAC-threshold configuring scheme, the proposed architecture performs conversions in two-stages, similarly to pipelined ADCs. An additi ...

2018