A DAC Assisted Speed Enhancement Technique for High Resolution SAR ADC

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This paper presents a low-power single-channel 8-bit loop-unrolled (LU) successive approximation register (SAR) analog-to-digital-converter (ADC) with a novel common-mode adaptive background comparator offset calibration scheme. LU-SAR ADCs use multiple co ...

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A Successive Approximation Register Analog-to-Digital Converter (SAR ADC) comprising a Track-and-Hold (T/H) switch configured for a sampling of an input voltage in the form of charge onto a capacitor; a Capacitive Digital-to- Analog Converter (CD AC) opera ...

Ultralow-power sensing with inference functionality embedded in sensor nodes is essential for enabling the emerging pervasive intelligence. For acoustic inference sensing, the feature extraction can take advantage of power-efficient analog circuits. Howeve ...

This paper presents a 9-bit 222 MS/s low-power asynchronous single-bit/cycle successive approximation register (SAR) ADC. The SAR ADC combines techniques such as asynchronous clocking, binary-weighted custom-designed capacitive DAC with small unit capacito ...

One of the greatest challenges in the design of modern wearable devices is energy efficiency. While data processing and communication have received a lot of attention from the industry and academia, leading to highly efficient microcontrollers and transmis ...

The demand on high speed Analog to Digital Converters (ADCs) has increased considerably the last years. From communications circuit to high speed oscilloscopes, Giga Samples per second (GS/s) ADCs are requested. With the scaling of the CMOS technology, des ...

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This paper presents a low power successive approximation register (SAR) ADC and its front-end automatic gain control (AGC) amplifier designed in 65nm CMOS technology. Digitally controlled variable gain amplifier (VGA) in AGC loop is used to maximize the dy ...

In this paper, a novel SAR ADC architecture enabling very high speed operation is presented. Based on a hybrid capacitive DAC-threshold configuring scheme, the proposed architecture performs conversions in two-stages, similarly to pipelined ADCs. An additi ...

A DAC Assisted Speed Enhancement Technique for High Resolution SAR ADC

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