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Alexandre Sébastien Julien Levisse

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Publications associées (37)

A Hybrid Cache HW/SW Stack for Optimizing Neural Network Runtime, Power and Endurance

David Atienza Alonso, William Andrew Simon, Marina Zapater Sancho, Alexandre Sébastien Julien Levisse

Hybrid caches consisting of both SRAM and emerging Non-Volatile Random Access Memory (eNVRAM) bitcells increase cache capacity and reduce power consumption by taking advantage of eNVRAM's small area footprint and low leakage energy. However, they also inhe ...

2020

Blade: An in-Cache Computing Architecture for Edge Devices

David Atienza Alonso, William Andrew Simon, Marina Zapater Sancho, Yasir Mahmood Qureshi, Alexandre Sébastien Julien Levisse, Marco Antonio Rios

Area and power constrained edge devices are increasingly utilized to perform compute intensive workloads, necessitating increasingly area and power efficient accelerators. In this context, in-SRAM computing performs hundreds of parallel operations on spati ...

2020

Exploration Methodology for BTI-Induced Failures on RRAM-Based Edge AI Systems

David Atienza Alonso, Miguel Peon Quiros, Alexandre Sébastien Julien Levisse, Marco Antonio Rios

Resistive switching memory technologies (RRAM) are seen by most of the scientific community as an enabler for Edge-level applications such as embedded deep Learning, AI or signal processing of audio and video signals. However, going beyond a "simple'' repl ...

IEEE2020

Towards Deeply Scaled 3D MPSoCs with Integrated Flow Cell Array Technology

David Atienza Alonso, Mohamed Mostafa Sabry Aly, Halima Najibi, Marina Zapater Sancho, Alexandre Sébastien Julien Levisse

Deeply-scaled three-dimensional (3D) Multi-Processor Systems-on-Chip (MPSoCs) enable high performance and massive communication bandwidth for next-generation computing. However, as process nodes shrink, temperature-dependent leakage dramatically increases, ...

2020

Write Termination circuits for RRAM : A Holistic Approach From Technology to Application Considerations

David Atienza Alonso, Alexandre Sébastien Julien Levisse, Marco Antonio Rios

While Resistive Random Access Memories (RRAM) are perceived nowadays as a promising solution for the future of computing, these technologies suffer from intrinsic variability regarding programming voltage, switching speed and achieved resistance values. Wr ...

IEEE2020

Analysis of Functional Errors Produced by Long-Term Workload-Dependent BTI Degradation in Ultra-Low Power Processors

David Atienza Alonso, Ruben Braojos Lopez, Loris Gérard Duch, Miguel Peon Quiros, Alexandre Sébastien Julien Levisse

Aging effects in digital circuits change the switching characteristics of their transistors, resulting in timing violations that can lead to functional errors at the system level. In particular, BTI is a degradation effect that changes the threshold voltag ...

2020

RRAM-VAC: A Variability-Aware Controller for RRAM-based Memory Architectures

David Atienza Alonso, Alexandre Sébastien Julien Levisse, Marco Antonio Rios, Shikhar Tuli

The growing need for connected, smart and energy efficient devices requires them to provide both ultra-low standby power and relatively high computing capabilities when awoken. In this context, emerging resistive memory technologies (RRAM) appear as a prom ...

2020

BLADE: A BitLine Accelerator for Devices on the Edge

David Atienza Alonso, William Andrew Simon, Marina Zapater Sancho, Yasir Mahmood Qureshi, Alexandre Sébastien Julien Levisse

The increasing ubiquity of edge devices in the consumer market, along with their ever more computationally expensive workloads, necessitate corresponding increases in computing power to support such workloads. In-memory computing is attractive in edge devi ...

2019

A Fast, Reliable and Wide-voltage-range In-memory Computing Architecture

David Atienza Alonso, William Andrew Simon, Marina Zapater Sancho, Alexandre Sébastien Julien Levisse

In-Memory Computing (IMC) solutions, and particularly bitline computing in SRAM, appear promising as they mitigate one of the most energy consuming aspects in computation: data movement. In this work we propose a fast (2.4Ghz for bitwise operations and 2.4 ...

Association for Computing Machinery2019

RRAMSpec: A Design Space Exploration Framework for High Density Resistive RAM

Alexandre Sébastien Julien Levisse

Resistive RAM (RRAM) is a promising emerging Non-Volatile Memory candidate due to its scalability and CMOS compatibility, which enables the fabrication of high density RRAM crossbar arrays in Back-End-Of-Line CMOS processes. Fast and accurate architectural ...

2019

Functionality Enhanced Memories for Edge-AI Embedded Systems

David Atienza Alonso, Pierre-Emmanuel Julien Marc Gaillardon, William Andrew Simon, Alexandre Sébastien Julien Levisse, Marco Antonio Rios

With the surge in complexity of edge workloads, it appeared in the scientific community that such workloads cannot be anymore overflown to the cloud due to the huge edge device to server communication energy cost and the high energy consumption induced in ...

IEEE2019

Switching event detection and self-termination programming circuit for energy efficient ReRAM memory arrays

Etienne Nowak, Alexandre Sébastien Julien Levisse

Energy efficiency remains a challenge for the design of non-volatile resistive memories (ReRAMs) arrays. This memory technology suffers from intrinsic variability in switching speed, programming voltages and resistance levels. The programming conditions of ...

2019

RRAMSpec: A Design Space Exploration Framework for High Density Resistive RAM

Alexandre Sébastien Julien Levisse

2019

A Design Framework for Thermal-Aware Power Delivery Network in 3D MPSoCs with Integrated Flow Cell Arrays

Halima Najibi, Marina Zapater Sancho, Alexandre Sébastien Julien Levisse

Integrated Flow Cell Array (FCA) technology promises to address the power delivery and heat dissipation challenges in three-dimensional Multi Processor Systems-on-Chips (3D MPSoCs) by providing combined inter-tier liquid cooling and power generation capabi ...

2019

An Associativity-Agnostic in-Cache Computing Architecture Optimized for Multiplication

David Atienza Alonso, William Andrew Simon, Marina Zapater Sancho, Alexandre Sébastien Julien Levisse, Marco Antonio Rios

With the spread of cloud services and Internet of Things concept, there is a popularization of machine learning and artificial intelligence based analytics in our everyday life. However, an efficient deployment of these data-intensive services requires per ...

2019

RRAM Crossbar Arrays for Storage Class Memory Applications : Throughput and Density Considerations

Alexandre Sébastien Julien Levisse

As more and more high density memories are required to satisfy the Internet of Things ecosystem, academics and industrials are looking for an intermediate solution to fill the gap between DRAM and Flash NAND in the memory hierarchy. The emergence of Resist ...

2018

Resistive Switching Memory Architecture Based on Polarity Controllable Selectors

Pierre-Emmanuel Julien Marc Gaillardon, Alexandre Sébastien Julien Levisse

With the continuous scaling of CMOS technology, integrating an embedded high-density non-volatile memory appears to be more and more costly and technologically challenging. Beyond floating-gate memory technologies, bipolar resistive random access memories ...

2018

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