Alexandre Sébastien Julien Willommet

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With the continuous scaling of CMOS technology, integrating an embedded high-density non-volatile memory appears to be more and more costly and technologically challenging. Beyond floating-gate memory technologies, bipolar resistive random access memories ...

We present an error correction code (ECC) decoder based on the Guessing Random Additive Noise Decoding (GRAND) with ABandonment (GRANDAB) algorithm for applications that require constant throughput and fixed decoding latency in the Gbps range. This high co ...

Resistive RAM (RRAM) is a promising emerging Non-Volatile Memory candidate due to its scalability and CMOS compatibility, which enables the fabrication of high density RRAM crossbar arrays in Back-End-Of-Line CMOS processes. Fast and accurate architectural ...

Edge devices must support computationally demanding algorithms, such as neural networks, within tight area/energy budgets. While approximate computing may alleviate these constraints, limiting induced errors remains an open challenge. In this paper, we pro ...

Inferences using Convolutional Neural Networks (CNNs) are resource and energy intensive. Therefore, their execution on highly constrained edge devices demands the careful co-optimization of algorithms and hardware. Addressing this challenge, in this paper ...

Flow cell arrays (FCAs) concurrently provide efficient on-chip liquid cooling and electrochemical power generation. This technology is especially promising for three-dimensional multi-processor systems-on-chip (3D MPSoCs) realized in deeply scaled technolo ...

Flow cell arrays (FCAs) provide efficient on-chip liquid cooling and electrochemical power generation capabilities in three-dimensional multi-processor systems-on-chip (3DMPSoCs). When connected to power delivery networks (PDNs) of chips, the current flowi ...

With the surge in complexity of edge workloads, it appeared in the scientific community that such workloads cannot be anymore overflown to the cloud due to the huge edge device to server communication energy cost and the high energy consumption induced in ...

Aging effects in digital circuits change the switching characteristics of their transistors, resulting in timing violations that can lead to functional errors at the system level. In particular, BTI is a degradation effect that changes the threshold voltag ...

A random access memory having a memory array having a plurality of local memory groups, each local memory group including a plurality of bitcells arranged in a bitcell column, a pair of local bitlines operatively connected to the plurality of bitcells, a p ...

This paper presents the set of simulation means used to develop the concept of N2C2 (neural network compute cube) based on a vertical transistor technology platform. On the basis of state-of-the-art junctionless nanowire transistors (JLNT), TCAD simulation ...

A random access memory array including a plurality of local memory group ways, each local memory group way including, a plurality of local memory groups, each local memory group including, a memory column including a plurality of memory cells, a pair of lo ...

Machine learning algorithms such as Convolutional Neural Networks (CNNs) are characterized by high robustness towards quantization, supporting small-bitwidth fixed-point arithmetic at inference time with little to no degradation in accuracy. In turn, small ...

While Resistive Random Access Memories (RRAM) are perceived nowadays as a promising solution for the future of computing, these technologies suffer from intrinsic variability regarding programming voltage, switching speed and achieved resistance values. Wr ...

Area and power constrained edge devices are increasingly utilized to perform compute intensive workloads, necessitating increasingly area and power efficient accelerators. In this context, in-SRAM computing performs hundreds of parallel operations on spati ...

Alexandre Sébastien Julien Willommet

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Resistive Switching Memory Architecture Based on Polarity Controllable Selectors

A GRANDAB Decoder with 8.48 Gbps Worst-Case Throughput in 65nm CMOS

RRAMSpec: A Design Space Exploration Framework for High Density Resistive RAM

Exact Neural Networks from Inexact Multipliers via Fibonacci Weight Encoding

A Flexible In-Memory Computing Architecture for Heterogeneously Quantized CNNs

Thermal and Voltage-Aware Performance Management of 3D MPSoCs with Flow Cell Arrays and Integrated SC Converters

Enabling Optimal Power Generation of Flow Cell Arrays in 3D MPSoCs with On-Chip Switched Capacitor Converters

RRAMSpec: A Design Space Exploration Framework for High Density Resistive RAM

Functionality Enhanced Memories for Edge-AI Embedded Systems

Analysis of Functional Errors Produced by Long-Term Workload-Dependent BTI Degradation in Ultra-Low Power Processors

Memory chip or memory array for wide-voltage range in-memory computing using bitline technology

Modelling of vertical and ferroelectric junctionless technology for efficient 3D neural network compute cube dedicated to embedded artificial intelligence

Associativity-agnostic in-cache computing memory architecture optimized for multiplication

DBFS: Dynamic Bitwidth-Frequency Scaling for Efficient Software-defined SIMD

Write Termination circuits for RRAM : A Holistic Approach From Technology to Application Considerations

Blade: An in-Cache Computing Architecture for Edge Devices