Publications de Xifan Tang | EPFL Graph Search

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Field Programmable Gate Arrays (FPGAs) can benefit non-volatility and high-performance by exploiting Resistive Random Access Memories (RRAMs). In RRAM-based FPGAs, the memories do not only replace the SRAMs and store configurations, but they can also repla ...

Routing multiplexers based on pass-transistors or transmission gates are an essential components in many digital integrated circuits. However, whatever structure is employed, CMOS multiplexers have two major limitations: 1) their delay is linearly related ...

Hard-wired carry chains in FPGAs are designed to improve efficiency of important arithmetic primitives. Although they are proven to be effective for arithmetic-rich functions, there are very few studies on the optimization opportunities of carry chains for ...

In this paper, we developed a simulation-based architecture evaluation framework for field-programmable gate arrays (FPGAs), called FPGA-SPICE, which enables automatic layout-level estimation and electrical simulations of FPGA architectures. FPGA-SPICE can ...

Clock distribution networks are affected by different sources of variations. The resulting clock uncertainty significantly affects the frequency of a circuit. To support this analysis, a statistical model of skitter, which consists of clock skew and jitter ...

The routing architecture, heavily using programmable switches, dominates the area, delay and power of Field Programmable Gate Arrays (FPGAs). Resistive Random Access Memories (RRAMs) enable high-performance routing architectures through the r ...

Field Programmable Gate Arrays (FPGAs) have been indispensable components of embedded systems and datacenter infrastructures. However, energy efficiency of FPGAs has become a hard barrier preventing their expansion to more application contexts, due to two ...

Resistive Random Access Memory (RRAM) technology opens the opportunity for granting both high-performance and low- power features to routing multiplexers. In this paper, we study the physical design considerations related to RRAM- based routing mult ...

Clock distribution networks consume a considerable portion of the power dissipated by synchronous circuits. In conventional clock distribution networks, clock buffers are inserted to retain signal integrity along the long interconnects, which, in turn, sig ...

Resistive random access memory (RRAM) based multiplexers and field programmable gate arrays (FPGAs) are provided. The RRAM-based multiplexers and FPGAs include a 4T1R programming structure to program the RRAMs. The programming structure includes two progra ...

Compared to Application-Specific Integrated Circuits (ASICs), Field Programmable Gate Arrays (FPGAs) provide reconfigurablity at the cost of lower performance and higher power consumption. Exploiting a large number of programmable switche ...

Silicon nanowire transistors with Schottky-barrier contacts exhibit both n-type and p-type characteristics under different bias conditions. Polarity controllability of silicon nanowire transistors has been further demonstrated by using an additional polari ...

Static Random Access Memory (SRAM)-based routing multiplexers, whatever structure is employed, share a common limitation: their area, delay and power increase linearly with the input size. This property results in most SRAM-based FPGA architectures ...

Resistive Random Access Memory (RRAM)-based FPGAs are predicted to outperform conventional FPGAs architectures in area, delay and power over a wide range of voltage operations, allowing novel energy-quality trade-offs for reconfigurable computing. The oppo ...

In this paper, we investigate the opportunity brought by controllable-polarity transistors to design efficient reconfigurable circuits. Controllable-polarity transistors are devices whose polarity can be electrostatically programmed to be either n- or p-ty ...

A routing architecture for fast interconnections between Look-Up Tables (LUTs) in a group of Basic Logic Elements (BLEs), whereby a size of the group ranges from 1 to k+1, where k is the number of inputs of a LUT, and LUTs in the group are indexed from 1 t ...

True Single-Phase Clock (TSPC) Flip-Flops, based on dynamic logic implementation, are area-saving and high-speed compared to standard static flip-flops. Furthermore, logic gates can be embedded into TSPC flip-flops which significantly improves performance. ...

In classical FPGA, LUTs and DFFs are pre-packed into BLEs and then BLEs are grouped into logic blocks. We propose a novel logic block architecture with fast combinational paths between LUTs, called pattern-based logic blocks. A new clustering algorithm is ...

Resistive Random Access Memory (RRAM)-based routing multiplexers, built using a one-level structure, are significantly more delay efficient than state-of-art SRAM-based implementations thanks to their lower achievable on-state resistance. In addition, the ...

Nowadays, Field Programmable Gate Arrays (FPGA) exploit Look-Up Tables (LUTs) to generate logic functions. A K-input LUT can implement any Boolean functions with K inputs. Thanks to this flexibility, LUTs remained concep ...

Xifan Tang

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A Study on the Programming Structures for RRAM-based FPGA Architectures

Circuit Designs of High-Performance and Low-Power RRAM-Based Multiplexers Based on 4T(ransistor)1R(RAM) Programming Structure

Improving Circuit Mapping Performance Through MIG-based Synthesis for Carry Chains

FPGA-SPICE: A Simulation-Based Architecture Evaluation Framework for FPGAs

Timing Uncertainty in 3-D Clock Trees due to Process Variations and Power Supply Noise

A High-Performance Low-Power Near-Vt RRAM-based FPGA

Circuit Design, Architecture and CAD for RRAM-based FPGAs

Physical Design Considerations of One-level RRAM-based Routing Multiplexers

An Enhanced Design Methodology for Resonant Clock Trees

Resistive random access memory based multiplexers and field programmable gate arrays

A Study on Buffer Distribution for RRAM-based FPGA Routing Structures

Configurable Circuits Featuring Dual-Threshold-Voltage Design With Three-Independent-Gate Silicon Nanowire FETs

Optimization Opportunities in RRAM-based FPGA Architectures

Post-P&R Performance and Power Analysis for RRAM-based FPGAs

A Novel FPGA Architecture based on Ultra-Fine Grain Reconfigurable Logic Cells

Pattern-based fpga logic block and clustering algorithm

TSPC Flip-Flop Circuit Design with Three-Independent-Gate Silicon Nanowire FETs

Pattern-Based FPGA Logic Block and Clustering Algorithm

A High-performance FPGA Architecture Using One-Level RRAM-based Multiplexers

Towards More Efficient Logic Blocks by Exploiting Biconditional Expansion