Publications de Arnab Biswas | EPFL Graph Search

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We report a novel device which exploits the internally combined quantum mechanical Band-To-Band and Barrier Tunneling mechanisms to achieve improved performances and overcome the intrinsic low current drive limitations of conventional Tunnel FETs and the 6 ...

This paper reports a compact ambipolar model for homojunction strained-silicon (sSi) nanowire (NW) tunnel FETs (TFETs) capable of accurately describing both I-V and G-V characteristics in all regimes of operation, n- and p-ambipolarity, the superlinear ons ...

Aggressive scaling of the supply voltage reduces the energy needed for switching of standard CMOS devices. However, advanced CMOS technologies are facing two main problems that consequently lead to higher power consumption: the complexity of a further supp ...

In this work we propose and demonstrate the use of a Tunnel FET (TFET) as capacitorless DRAM cell based on TCAD simulations and experiments. We report more experimental results on Tunnel FETs implemented as a double-gate (DG) fully-depleted Silicon-On-Insu ...

We report a simulation-based study of an all-silicon novel device which exploits internally combined quantum mechanical band-to-band and barrier tunneling mechanisms to overcome the intrinsic low current drive limitations of conventional silicon Tunnel FET ...

The aim of this work has been the investigation of homo-junction Tunnel Field Effect Transistors starting from a compact modelling perspective to its possible applications. Firstly a TCAD based simulation study is done to explain the main device characteri ...

This letter proposes a hybrid abrupt switch principle and a corresponding device architecture that combines quantum mechanical band-to-band and barrier tunneling mechanisms. The device overcomes the intrinsically low on-current (I-ON) of conventional tunne ...

There are several techniques for junction profiling available in literature, yet none of them are practically suitable for the accurate determination of the lateral junction steepness in TFET devices, which is the most important parameter influencing TFET ...

This paper reports a simulation based study of the non-local tunneling model using a commercially available technology computer-aided design (TCAD) device simulator. Single gate Tunnel FET devices with 400nm gate length based on SOI technology are measured ...

In this work, the conformal mapping technique is applied to obtain an analytical closed form solution of the 2D Poisson’s equation for a double-gate Tunnel FET. The generated band profiles are accurate in all regions of device operation. Furthermore, the c ...

A tunnel field effect transistor (TFET), including a source region, a gate region, a channel region, and a drain region, the gate region including a gate stack, wherein an area of the source region that is facing the channel region is overlapped by the gat ...

A single field effect transistor capacitor-less memory device, and method of operating the same, including a drain region, a source region, an intrinsic channel region between the drain region and the source region forming the single field effect transisto ...

In this work, a compact model based on an analytical closed form solution of the 1D Poisson's equation for a double-gate Tunnel FET is derived. Furthermore, the current levels are estimated by implementing an algorithm based on the Kane's band-to-band tunn ...

Tunneling Field Effect Transistors (TFET) are promising devices to respond to the demanding requirements of future technology nodes. The benefits of the TFETs are linked to their sub-60mV/decade sub-threshold swing, a prerequisite for scaling the supply vo ...

Steep-slope transistors allow to scale down the supply voltage and the energy per computed bit of information as compared to conventional field-effect transistors (FETs), due to their sub-60 mV/decade subthreshold swing at room temperature. Currently pursu ...

In this work we report experimental results on the use of Tunnel Field-Effect Transistors (TFET) as capacitorless Dynamic Random Access Memory (DRAM) cells, implemented as a double-gate (DG) Fully-Depleted Silicon-On-Insulator (FD-SOI) devices. The devices ...

Arnab Biswas

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Abrupt switch based on internally combined Band-To-Band and Barrier Tunneling mechanisms

Benchmarking of Homojunction Strained-Si NW Tunnel FETs for Basic Analog Functions

Compact Modeling of Homojunction Tunnel FETs

1T Capacitor-less DRAM cell based on asymmetric Tunnel FET design

Abrupt switch based on internally combined band-to-band and barrier tunneling mechanisms

Tunnel Field Effect Transistors : from Steep-Slope Electronic Switches to Energy Efficient Logic Applications

A tunneling field-effect transistor exploiting internally combined band-to-band and barrier tunneling mechanisms

A Novel Extraction Method and Compact Model for the Steepness Estimation of FDSOI TFET Lateral Junction

TCAD Simulation of SOI TFETs and Calibration of Non-local Band-to-Band Tunneling Model

Study of Fin-Tunnel FETs with doped pocket as Capacitor-less 1T DRAM

Conformal Mapping Based DC Current Model For Double Gate Tunnel FETs

Tunnel fet based non-volatile memory boosted by vertical band-to-band tunneling

Single field effect transistor capacitor-less memory device and method of operating the same

Compact modeling of DG-Tunnel FET for Verilog-A implementation

New Tunnel-FET Architecture with Enhanced Ion and Improved Miller Effect for Energy Efficient Switching

A Steep-Slope Transistor Combining Phase-Change and Band-to-Band-Tunneling to Achieve a sub-Unity Body Factor

A study on 1T Capacitor-less Tunnel FET DRAM Exploiting Ungated Body

Investigation of Tunnel Field-Effect Transistors as a Capacitor-less Memory Cell

A capacitance-voltage model for DG-TFET