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Andreas Peter Burg

Cette personne a quitté l’EPFL

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Publications associées (207)

Page 1 sur 11

A Quality-Scalable and Energy-Efficient Approach for Spectral Analysis of Heart Rate Variability

David Atienza Alonso, Andreas Peter Burg, Georgios Karakonstantis, Mohamed Mostafa Sabry Aly, Aviinaash Sankaranarayanan

Today there is a growing interest in the integration of health monitoring applications in portable devices necessitating the development of methods that improve the energy efficiency of such systems. In this paper, we present a systematic approach that ena ...

IEEE2014

A Maximum-Likelihood-Based Two-User Receiver for LoRa Chirp Spread-Spectrum Modulation

Andreas Peter Burg, Alexios Konstantinos Balatsoukas Stimming, Orion Afisiadis, Joachim Tobias Tapparel

Long Range (LoRa) is an emerging low-power wide-area network technology offering long-range wireless connectivity to Internet of Things (IoT) devices. For energy efficiency reasons, LoRa end nodes implement a nonslotted ALOHA multiple access scheme to tran ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2022

Data Compression via Logic Synthesis

Giovanni De Micheli, Andreas Peter Burg, Pierre-Emmanuel Julien Marc Gaillardon, Luca Gaetano Amarù

Nowadays, most software and hardware applications are committed to reduce the footprint and resource usage of data. In this general context, lossless data compression is a beneficial technique that encodes information using fewer (or at most equal number o ...

2014

An Energy-Autonomous Wireless Sensor With Simultaneous Energy Harvesting and Ambient Light Sensing

Andreas Peter Burg, Catherine Dehollain, Roberto La Rosa

Wireless sensor nodes (WSNs) are generally powered by batteries, which results in a substantial limitation to the places where the nodes can be installed, to the maximum number of deployable devices, and to the node lifetime. To meet the demand for Interne ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2021

GC-eDRAM With Body-Bias Compensated Readout and Error Detection in 28-nm FD-SOI

Andreas Peter Burg, Adam Shmuel Teman, Robert Giterman, Andrea Bonetti

Gain-cell embedded DRAM (GC-eDRAM) is an attractive alternative to conventional SRAM due to its high-density, low-leakage, and inherent two-ported functionality. However, its dynamic storage mechanism requires power-hungry refresh cycles to maintain data. ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2019

E2CNN: Ensembles of Convolutional Neural Networks to Improve Robustness Against Memory Errors in Edge-Computing Devices

David Atienza Alonso, Andreas Peter Burg, Miguel Peon Quiros, Flavio Ponzina

To reduce energy consumption, it is possible to operate embedded systems at sub-nominal conditions (e.g., reduced voltage, limited eDRAM refresh rate) that can introduce bit errors in their memories. These errors can affect the stored values of CNN weights ...

2021

A 161-mW 56-Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14-nm FinFET

Yusuf Leblebici, Andreas Peter Burg, Alessandro Cevrero, Thomas Toifl, Lukas Kull, Ilter Ozkaya, Gain Kim, Cosimo Aprile

This article introduces a wireline receiver (RX) data-path employing discrete multi-tone (DMT) modulation for communicating over electrical links. The DMT RX incorporates a fully digital equalization data-path, with a synthesized and automatically placed a ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2020

Gain-Cell Embedded DRAMs: Modeling and Design Space

Andreas Peter Burg, Robert Giterman, Andrea Bonetti, Adam Shmuel Teman

Among the different types of dynamic random-access memories (DRAMs), gain-cell embedded DRAM (GC-eDRAM) is a compact, low-power, and CMOS-compatible alternative to conventional static random-access memory (SRAM). GC-eDRAM achieves high memory density, as i ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2020

A ReRAM-Based Non-Volatile Flip-Flop with Sub-VT Read and CMOS Voltage-Compatible Write

Giovanni De Micheli, Andreas Peter Burg, Davide Sacchetto, Pierre-Emmanuel Julien Marc Gaillardon, Pascal Andreas Meinerzhagen

The total power budget of Ultra-Low Power (ULP) VLSI Systems-on-Chip (SoCs) is often dominated by the leakage power of embedded memories and pipeline registers, which typically cannot be power-gated during sleep periods as they need to retain data and prog ...

2013

A High Dynamic Range Envelop Detector for Heterodyne Receiver Architecture

Andreas Peter Burg, Catherine Dehollain

Energy detection (ED) has been of interest for various applications ranging from very low frequency biomedical signal read-out to high frequency wireless communication. The analog implementation of the ED requires circuits with a non-linear transfer charac ...

Ieee-Inst Electrical Electronics Engineers Inc2024

4T Gain-Cell with internal-feedback for ultra-low retention power at scaled CMOS nodes

Andreas Peter Burg, Adam Shmuel Teman, Pascal Andreas Meinerzhagen, Robert Giterman

Gain-Cell embedded DRAM (GC-eDRAM) has recently been recognized as a possible alternative to traditional SRAM. While GC-eDRAM inherently provides high-density, low-leakage, low-voltage, and 2-ported operation, its limited retention time requires periodic, ...

IEEE2014

Method and apparatus for low complexity spectral analysis of bio-signals

David Atienza Alonso, Andreas Peter Burg, Srinivasan Murali, Georgios Karakonstantis, Aviinaash Sankaranarayanan

A method and device for reducing the computational complexity of a processing algorithm, of a discrete signal, in particular of the spectral estimation and analysis of bio-signals, with minimum or no quality loss, which comprises steps of (a) choosing a do ...

2015

An FPGA-Based 4 Mbps Secret Key Distillation Engine for Quantum Key Distribution Systems

Andreas Peter Burg, Pascal Junod, Jeremy Hugues-Felix Constantin, Nicholas Alexander Preyss

Quantum key distribution (QKD) enables provably secure communication between two parties over an optical fiber that arguably withstands any form of attack. Besides the need for a suitable physical signalling scheme and the corresponding devices, QKD also r ...

Springer2017

A 16-kB 65-nm GC-eDRAM Macro With Internal Bias Voltage Generation Providing Over 100-μs Retention Time

Andreas Peter Burg, Halil Andac Yigit

Gain-cell embedded dynamic random access memory (GC-eDRAM) has emerged as a suitable choice for embedded memory implementation due to its high density, low leakage current, and voltage scaling compatibility. This work presents a 16-kB 3T-1C GC-eDRAM macro, ...

2024

Improving Railway Track Coverage with mmWave Bridges: A Measurement Campaign

Andreas Peter Burg, Ruben Merz, Adrian Schumacher

Bringing cellular capacity into modern trains is challenging because they act as Faraday cages. Building a radio frequency (RF) corridor along the railway tracks ensures a high signal-to-noise ratio and limits handovers. However, building such RF corridors ...

ASSOC COMPUTING MACHINERY2021

Ultra Low Voltage Synthesizable Memories: A Trade-Off Discussion in 65 nm CMOS

Andreas Peter Burg, Pascal Andreas Meinerzhagen, Oskar Andersson

In this study, design considerations for ultra low voltage (ULV) standard-cell based memories (SCM) are presented. Trade-offs for area cost, leakage power, access time, and access energy are discussed and realized using different read logic styles, latch a ...

Institute of Electrical and Electronics Engineers2016

Dynamic SCL Decoder With Path-Flipping for 5G Polar Codes

Andreas Peter Burg, Alexios Konstantinos Balatsoukas Stimming, Yifei Shen

Since polar were ratified as part of the 5G standard, low-complexity polar decoders with close-to-optimum error-rate performance have received significant attention. Compared to successive cancellation (SC) decoding, both SC list and SC flip decoding can i ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2022

Polarization-Adjusted Convolutional (PAC) Codes: Sequential Decoding vs List Decoding

Andreas Peter Burg

In the Shannon lecture at the 2019 International Symposium on Information Theory (ISIT), Arikan proposed to employ a one-to-one convolutional transform as a pre-coding step before the polar transform. The resulting codes of this concatenation are called po ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2021

Low-power processor architecture exploration for online biomedical signal analysis

David Atienza Alonso, Andreas Peter Burg, Luca Benini, Jeremy Hugues-Felix Constantin, Ahmed Yasir Dogan

In this study, the authors explore sequential and parallel processing architectures, utilising a custom ultra-low-power (ULP) processing core, to extend the lifetime of health monitoring systems, where slow biosignal events and highly parallel computations ...

Inst Engineering Technology-Iet2012

Design Techniques for High-Speed Multi-Level Viterbi Detectors and Trellis-Coded-Modulation Decoders

Andreas Peter Burg, Thomas Toifl, Lukas Kull

The implementation of a 25.6-Gb/s four-level pulse-amplitude-modulation (4-PAM) reduced-state sliding-block Viterbi detector (VD) is presented. The power consumption of the VD is 105 orilV at a supply voltage of 0.7 V, corresponding to an energy efficiency ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2018