Publications de Antonio Pullini

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This paper presents a lightweight cryptographic system integrated onto a multi-function implantable biosensor prototype. The resulting heterogeneous system provides a unique and fundamental capability by immediately encrypting and signing the sensor data u ...

The quest for technologies with superior device characteristics has showcased Carbon Nanotube Field Effect Transistors (CNFETs) into limelight. Among the several design aspects necessary for today’s grail in CNFET technology, achieving functional immunity ...

Nanometer CMOS scaling has resulted in greatly increased circuit variability, with extremely adverse consequences on design predictability and yield. A number of recent works have focused on adaptive post-fabrication tuning approaches to mitigate this prob ...

With technology scaling, the wire delay as a fraction of the total delay is increasing, and the communication architecture is becoming a major bottleneck for system performance in systems on chip (SoCs). A communication-centric design paradigm, networks on ...

With the growing complexity in consumer embedded products, new tendencies forecast heterogeneous Multi-Processor Systems-On-Chip (MPSoCs) consisting of complex integrated components communicating with each other at very high-speed rates. Intercommunication ...

Research on Networks on Chips (NoCs) has spanned over a decade and its results are now visible in some products. Thus the seminal idea of using networking technology to address the chip-level interconnect problem has been shown to be correct. Moreover, as ...

The IronIC project has the aim of developing a fully implantable and remotely powered platform for the real- time monitoring of human metabolites. In this paper we present a mixed-signal interface IC for the electrochemical sensing data acquisition chain. ...

On-chip wires are becoming unreliable as the effect of various noise sources increases with technology scaling. This leads to unpredictable timing delay variations on the interconnect wires. There is a significant need to mitigate the effect of parasitics ...

As embedded computing evolves towards ever more powerful architectures, the challenge of properly interconnecting large numbers of on-chip computation blocks is becoming prominent. Networks-on-Chip (NoCs) have been proposed as a scalable solution to both p ...

Very deep submicron process technologies are ideal application fields for NoCs, which offer a promising solution to the scalability problem. This article sheds light on the benefits and challenges of Noc-Based interconnect design in nanometer CMOS. The aut ...

Antonio Pullini

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A Lightweight Cryptographic System for Implantable Biosensors

Design of Compact Imperfection-Immune CNFET Layouts for Standard-Cell-Based Logic Synthesis

Physically clustered Forward Body Biasing for variability compensation in nanometer CMOS design

Physically clustered forward body biasing for variability compensation in nanometer CMOS design

Timing-Error-Tolerant Network-on-Chip Design Methodology

Network-On-Chip Design and Synthesis Outlook

Networks on Chips: From Research to Products

Sub-mW Reconfigurable Interface IC for Electrochemical Sensing

Comparison of a Timing-Error Tolerant Scheme with a Traditional Re-transmission Mechanism for Networks on Chips

NoC Design and Implementation in 65 nm Technology

Bringing NoCs to 65nm