Publications de Alessandro Cevrero

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This paper presents a parallel implementation technique of digital equalizer for high-speed wireline serial link receiver (RX). In wireline RX, inter-symbol interference (ISI) is mitigated by continuous-time linear equalizer, and the remaining ISI is cance ...

This paper presents a circuit-level design and analysis of high-data-rate 3D serial vertical links which exploit the high bandwidth provided by TSV technology. As most of the existing TSVs consume a large amount of die area, the serial configuration can sa ...

An innovative modular 3-D stacked multi-processor architecture is presented. The platform is composed of completely identical stacked dies connected together by through-silicon-vias (TSVs). Each die features four 32-bit embedded processors and associated m ...

A 64-Gb/s high-sensitivity non-return to zero receiver (RX) data-path is demonstrated in the 14-nm-bulk FinFET CMOS technology. To achieve high sensitivity, the RX incorporates a transimpedance amplifier whose gain and bandwidth are co-optimized with a 1-t ...

3D integration can alleviate routing congestion, reducing the wirelength and improving performances. Nevertheless, each TSV still occupies non-negligible silicon area: as the number of TSV increases, their effect on the chip routing is detrimental. The red ...

We present a doubly parallelized layered quasi-cyclic low density parity-check decoder for the emerging IEEE 802.11ad multigigabit wireless standard. The decoding algorithm is equivalent to a nonparallelized layered decoder and, thus, retains its favorable ...

This work reports a low power implementation of a 60Gb/s NRZ optical receiver (RX) in 14nm bulk CMOS finFET featuring a first-order digital CDR with high jitter tolerance (JTOL). The design includes a single phase-rotator (PR) with low complexity control l ...

In this paper, we present a heterogeneous integration of ReRAMs with standard CMOS technology by post-processing the Back-End-of-the-Line (BEOL) of fully finished CMOS chips. ...

A novel modular, cost e ffective 3D multi-processor architecture is presented. Auto-configurable and independently testable identical dies are stacked exploiting Through-Silicon-Vias (TSV) technology, allowing to target different market segments by selecti ...

The Field Programmable Counter Array (FPCA) was introduced to improve FPGA performance for arithmetic circuits. An FPCA is a reconfigurable IP core that can be integrated into an FPGA. To exploit the FPCA, a circuit is transformed by merging disparate addi ...

A Generalized Programmable Counter Array (GPCA) is a reconfigurable multi-operand adder, which can be reprogrammed to sum a plurality of operands of arbitrary size. The GPCA is configured to compress the input words down to two operands using parallel coun ...

This paper proposes a novel technique to exploit the high bandwidth offered by through silicon vias (TSVs). In the proposed approach, synchronous parallel 3D links are replaced by serialized links to save silicon area and increase yield. Detailed analysis ...

A partially parallel low density parity check (LDPC) decoder compliant with the IEEE 802.3an standard for 10GBASE-T Ethernet is presented. The design is optimized for minimum silicon area and is based on the layered offset-min-sum algorithm which speeds up ...

We report a low-power 4-channel NRZ optical RX including a digital burst-mode CDR measured up to 40Gb/s/lane in 14nm CMOS. The RX, designed for 850nm VCSEL based optical links, can wake-up and achieve phase-lock in 8ns at BER

3D-ICs based on TSV technology provide high bandwidth inter-chip connections. The drawback is that most of the existing TSVs consume a large amount of silicon real estate. We present circuit-level design and analysis of area efficient, low power, high-data ...

This work describes a NRZ receiver data-path fabricated in 14nm bulk FinFET technology and characterized in an 850nm VCSEL based optical link up to 64Gb/s. It achieves 1.42pJ/bit energy efficiency while recovering PRBS-7 data (BER< 10-12) modulated by a VC ...

Alessandro Cevrero

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Parallel Implementation Technique of Digital Equalizer for Ultra-High-Speed Wireline Receiver

Design and Analysis of Jitter-Aware Low-Power and High-Speed TSV Links for 3D ICs

Design and Testing Strategies for Modular 3-D-Multiprocessor Systems Using Die-Level Through Silicon Via Technology

Advanced CMOS Circuits for Multi-Gb/s Links and 3D I/O Based on Through Silicon Via Technology

A 64-Gb/s 1.4-pJ/b NRZ Optical Receiver Data-Path in 14-nm CMOS FinFET

Impact of Data Serialization over TSVs on Routing Congestion in 3D-Stacked Multi-Core Processors

A Parallelized Layered QC-LDPC Decoder for IEEE 802.11ad

A 60 Gb/s 1.9 pJ/bit NRZ Optical-Receiver with Low Latency Digital CDR in 14nm CMOS FinFET

Heterogeneous integration of ReRAM crossbars in a CMOS foundry chip

Towards Cost Effective Multi-Core Processor Platforms Using 3-D Stacking Technology

Architectural improvements for field programmable counter arrays: enabling efficient synthesis of fast compressor trees on FPGAs

Generalized programmable counter arrays

Design and Feasibility of Multi-Gb/s Quasi-Serial Vertical Interconnects based on TSVs for 3D ICs

A 24-to-72GS/s 8b Time-Interleaved SAR ADC with 2.0-to-3.3pJ/conversion and > 30dB SNDR at Nyquist in 14nm CMOS FinFET

A 5.35 mm2 10GBASE-T Ethernet LDPC Decoder Chip in 90 nm CMOS

4x40 Gb/s 2 pJ/bit Optical RX with 8ns Power-on and CDR-Lock Time in 14nm CMOS

A 3D Stacked Multi-Core Processor Platform with Improved Testability

Low Power 3D Serial TSV Link for High Bandwidth Cross-Chip Communication

A 64Gb/s 1.4pJ/b NRZ Optical-Receiver Data-Path in 14nm CMOS FinFET

A 56Gb/s Burst-Mode NRZ Optical Receiver with 6.8ns Power-On and CDR-Lock Time for Adaptive Optical Links in 14nm FinFET CMOS