Alessandro Cevrero

Cette personne a quitté l’EPFL

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Publications associées (31)

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4x40 Gb/s 2 pJ/bit Optical RX with 8ns Power-on and CDR-Lock Time in 14nm CMOS

Alessandro Cevrero, Thomas Toifl, Ilter Ozkaya

We report a low-power 4-channel NRZ optical RX including a digital burst-mode CDR measured up to 40Gb/s/lane in 14nm CMOS. The RX, designed for 850nm VCSEL based optical links, can wake-up and achieve phase-lock in 8ns at BER

IEEE2018

A 3D Stacked Multi-Core Processor Platform with Improved Testability

Yusuf Leblebici, Alessandro Cevrero, Giulia Beanato, Panagiotis Athanasopoulos, Paolo Giovannini

2012

Low Power 3D Serial TSV Link for High Bandwidth Cross-Chip Communication

Giovanni De Micheli, Yusuf Leblebici, Alessandro Cevrero, Giulia Beanato

3D-ICs based on TSV technology provide high bandwidth inter-chip connections. The drawback is that most of the existing TSVs consume a large amount of silicon real estate. We present circuit-level design and analysis of area efficient, low power, high-data ...

2014

A 112Gb/s 2.6pJ/b 8-Tap FFE PAM-4 SST TX in 14nm CMOS

Alessandro Cevrero, Thomas Toifl, Lukas Kull, Ilter Ozkaya

IEEE2018

A 64Gb/s 1.4pJ/b NRZ Optical-Receiver Data-Path in 14nm CMOS FinFET

Yusuf Leblebici, Alessandro Cevrero, Thomas Toifl, Lukas Kull, Ilter Ozkaya

This work describes a NRZ receiver data-path fabricated in 14nm bulk FinFET technology and characterized in an 850nm VCSEL based optical link up to 64Gb/s. It achieves 1.42pJ/bit energy efficiency while recovering PRBS-7 data (BER< 10-12) modulated by a VC ...

Ieee2017

A 56Gb/s Burst-Mode NRZ Optical Receiver with 6.8ns Power-On and CDR-Lock Time for Adaptive Optical Links in 14nm FinFET CMOS

Yusuf Leblebici, Alessandro Cevrero, Thomas Toifl, Lukas Kull, Ilter Ozkaya

IEEE2018

Design Space Exploration for Field Programmable Compressor Trees

Yusuf Leblebici, Paolo Ienne, Philip Brisk, Alessandro Cevrero

2008

A 5.9mW/Gb/s 7Gb/s/pin 8-Lane Single-Ended RX with Crosstalk Cancellation Scheme using a XCTLE and 56-tap XDFE in 32nm SOI CMOS

Yusuf Leblebici, Volkan Cevher, Alessandro Cevrero, Thomas Toifl, Lukas Kull, Ilter Ozkaya, Cosimo Aprile

This work reports an 8-lane single-ended RX featuring compact and low power far-end crosstalk (FEXT) cancellation circuits. The RX data-path consists of a cross continuous-time linear equalizer (XCTLE) to remove FEXT by nearest aggressors within the channe ...

2015

Alessandro Cevrero

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4x40 Gb/s 2 pJ/bit Optical RX with 8ns Power-on and CDR-Lock Time in 14nm CMOS

A 3D Stacked Multi-Core Processor Platform with Improved Testability

Low Power 3D Serial TSV Link for High Bandwidth Cross-Chip Communication

A 112Gb/s 2.6pJ/b 8-Tap FFE PAM-4 SST TX in 14nm CMOS

A 64Gb/s 1.4pJ/b NRZ Optical-Receiver Data-Path in 14nm CMOS FinFET

A 56Gb/s Burst-Mode NRZ Optical Receiver with 6.8ns Power-On and CDR-Lock Time for Adaptive Optical Links in 14nm FinFET CMOS

Design Space Exploration for Field Programmable Compressor Trees

A 5.9mW/Gb/s 7Gb/s/pin 8-Lane Single-Ended RX with Crosstalk Cancellation Scheme using a XCTLE and 56-tap XDFE in 32nm SOI CMOS

3D-MMC: A Modular 3D Multi-Core Architecture with Efficient Resource Pooling

A 161mW 56Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14nm FinFET

Fast and Accurate BER Estimation Methodology for I/O Links based on Extreme Value Theory