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Srinivasan Murali

Cette personne a quitté l’EPFL

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Publications associées (45)

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Synthesis of Networks on Chips for 3D Systems on Chips

Giovanni De Micheli, Luca Benini, Srinivasan Murali, Ciprian Seiculescu

Three-dimensional stacking of silicon layers is emerging as a promising solution to handle the design complexity and heterogeneity of Systems on Chips (SoCs). Networks on Chips (NoCs) are necessary to efficiently handle the 3D interconnect complexity. Desi ...

2009

Networks on Chips: From Research to Products

Giovanni De Micheli, Luca Benini, Srinivasan Murali, Federico Angiolini, Ciprian Seiculescu

Research on Networks on Chips (NoCs) has spanned over a decade and its results are now visible in some products. Thus the seminal idea of using networking technology to address the chip-level interconnect problem has been shown to be correct. Moreover, as ...

2010

Reliability Support for On-chip Memories Using Networks-on-Chips

Giovanni De Micheli, David Atienza Alonso, Luca Benini, Srinivasan Murali, Federico Angiolini

As the geometries of the transistors reach the physical limits of operation, one of the main design challenges of Systems-on-Chips (SoCs) will be to provide dynamic (run-time) support against permanent and intermittent faults that can occur in the system. ...

2006

Method and Device for Non-Invasive Blood Pressure Measurement

David Atienza Alonso, Srinivasan Murali, Francisco Javier Rincon Vallejos, Alair Dias Junior

A system for measuring blood pressure of a user that comprises an ElectroCardioGram (ECG) circuit with at least two ECG electrodes configured to obtain an electrical activity of a heart of the user by measuring the electrical signals detected at the at lea ...

2017

Comparison of a Timing-Error Tolerant Scheme with a Traditional Re-transmission Mechanism for Networks on Chips

Giovanni De Micheli, David Atienza Alonso, Luca Benini, Srinivasan Murali, Federico Angiolini

On-chip wires are becoming unreliable as the effect of various noise sources increases with technology scaling. This leads to unpredictable timing delay variations on the interconnect wires. There is a significant need to mitigate the effect of parasitics ...

2006

A Method for Routing Packets Across Multiple Paths in NoCs with In-Order Delivery and Fault-Tolerance Guarantees

Giovanni De Micheli, David Atienza Alonso, Luca Benini, Srinivasan Murali

Networks on Chips (NoCs) are required to tackle the increasing delay and poor scalability issues of bus-based communication architectures. Many of today’s NoC designs are based on single path routing. By utilizing multiple paths for routing, congestion in ...

2007

NoC Design and Implementation in 65 nm Technology

Giovanni De Micheli, David Atienza Alonso, Luca Benini, Srinivasan Murali, Federico Angiolini

As embedded computing evolves towards ever more powerful architectures, the challenge of properly interconnecting large numbers of on-chip computation blocks is becoming prominent. Networks-on-Chip (NoCs) have been proposed as a scalable solution to both p ...

2007

Estimation of Blood Pressure and Pulse Transit Time Using Your Smartphone

David Atienza Alonso, Srinivasan Murali, Francisco Javier Rincon Vallejos, Alair Dias Junior

It is widely recognized today that there is an alarming rise of lifestyle-induced chronic diseases (e.g., type II diabetes) in our society. Therefore, a strong need exists for cost-effective and non-invasive devices that can measure blood pressure (BP) to ...

IEEE Computer Society Press2015

Diseño de redes en chip de propósito específico con información de rutado físico

Giovanni De Micheli, David Atienza Alonso, Luca Benini, Srinivasan Murali, Federico Angiolini

The equivalent English title: "Design of Custom Networks-on-Chip with Physical Layout Information" Abstract translated into English: Due to the growing demand of communication between processors and memory devices in Systems-on-Chip (SoCs), recently the ne ...

2006

Designing Best Effort Networks-on-Chip to Meet Hard Latency Constraints

Giovanni De Micheli, Luca Benini, Srinivasan Murali, Ciprian Seiculescu, Hamid Sarbazi-Azad, Dara Rahmati

Many classes of applications require Quality of Service (QoS) guarantees from the system interconnect. In Networks-on-Chip (NoC) QoS guarantees usually translate into bandwidth and latency constraints for the traffic flows and require hardware support in t ...

Assoc Computing Machinery2013

Processor Speed Control with Thermal Constraints

Giovanni De Micheli, David Atienza Alonso, Srinivasan Murali

We consider the problem of adjusting speeds of multiple computer processors, sharing the same thermal environment, such as a chip or multichip package. We assume that the speed of each processor (and associated variables such as power supply voltage) can b ...

2009

Routing Aware Switch Hardware Customization for Networks on Chips

Giovanni De Micheli, Srinivasan Murali

Networks on Chip (NoC) has been proposed as a scalable and reusable solution for interconnecting the ever- growing number of processor/memory cores on a single silicon die. As the hardware complexity of a NoC is significant, methods for designing a NoC wit ...

2006

A Method to Remove Deadlocks in Networks-on-Chips with Wormhole Flow Control

Giovanni De Micheli, Luca Benini, Srinivasan Murali, Ciprian Seiculescu

Networks-on-Chip (NoCs) are a promising interconnect paradigm to address the communication bottleneck of Systems-on-Chip (SoCs). Wormhole flow control is widely used as the transmission protocol in NoCs, as it offers high throughput and low latency. To mat ...

2010

A Multi-Path Routing Strategy with Guaranteed In-order Packet Delivery and Fault Tolerance for Networks on Chips

Giovanni De Micheli, David Atienza Alonso, Luca Benini, Srinivasan Murali

In this work we present a multi-path routing strategy that guarantees in-order packet delivery for Networks on Chips (NoCs). We present a design methodology that uses the routing strategy to optimally spread the traffic in the NoC to minimize the network b ...

2006

Computing Accurate Performance Bounds for Best Effort Networks-on-Chip

Giovanni De Micheli, Luca Benini, Srinivasan Murali, Federico Angiolini, Hamid Sarbazi-Azad, Dara Rahmati

Real-time (RT) communication support is a critical requirement for many complex embedded applications which are currently targeted to Network-on-chip (NoC) platforms. In this paper, we present novel methods to efficiently calculate worst- case bandwidth an ...

Institute of Electrical and Electronics Engineers2013

Early Wire Characterization for Predictable Network-on-Chip Global Interconnects

Giovanni De Micheli, Yusuf Leblebici, David Atienza Alonso, Srinivasan Murali, Ilhan Hatirnaz

This work envisions a common design methodology, applicable for every interconnect level and based on early wire characterization, to provide a faster convergence to a feasible and robust design. We claim that such a novel design methodology is vital for u ...

ACM Press New York, NY, US2007

Performance of the new SmartCardia wireless, wearable oximeter: a comparison with arterial SaO2 in healthy volunteers

Srinivasan Murali, Francisco Javier Rincon Vallejos

Background Our goal was to evaluate the performance of a new wearable arm located pulse oximeter. Methods Twelve volunteers were monitored with three pulse oximeters and underwent desaturation to 70% SaO(2). We compared the accuracy of SpO(2) reading from ...

BMC2022

Touch-Based System for Beat-to-Beat Impedance Cardiogram Acquisition and Hemodynamic Parameters Estimation

David Atienza Alonso, Srinivasan Murali, Francisco Javier Rincon Vallejos, Dionisije Sopic

Among all cardiovascular diseases, congestive heart failure (CHF) has a very high rate of hospitalization and mortality. In order to prevent hospitalization, there is a strong need to identify patients at risk of a CHF event by estimating a set of relevant ...

IEEE/ACM Press2016

SunFloor 3D: A Tool for Networks on Chip Topology Synthesis for 3D Systems on Chip

Giovanni De Micheli, Luca Benini, Srinivasan Murali, Ciprian Seiculescu

2009

A Method for Calculating Hard QoS Guarantees for Networks-on-Chip

Dara Rahmati, Giovanni De Micheli, Luca Benini, Srinivasan Murali, Federico Angiolini, Hamid Sarbazi-Azad

Many Networks-on-Chip (NoC) applications exhibit one or more critical traffic flows that require hard Quality of Service (QoS). Guaranteeing bandwidth and latency for such real time flows is crucial. In this paper, we present novel methods to efficiently c ...

2009