Publications by Srinivasan Murali

Chat with Graph Search

Ask any question about EPFL courses, lectures, exercises, research, news, etc. or try the example questions below.

DISCLAIMER: The Graph Chatbot is not programmed to provide explicit or categorical answers to your questions. Rather, it transforms your questions into API requests that are distributed across the various IT services officially administered by EPFL. Its purpose is solely to collect and recommend relevant references to content that you can explore to help you answer your questions.

Three-dimensional stacking of silicon layers is emerging as a promising solution to handle the design complexity and heterogeneity of Systems on Chips (SoCs). Networks on Chips (NoCs) are necessary to efficiently handle the 3D interconnect complexity. Desi ...

Research on Networks on Chips (NoCs) has spanned over a decade and its results are now visible in some products. Thus the seminal idea of using networking technology to address the chip-level interconnect problem has been shown to be correct. Moreover, as ...

As the geometries of the transistors reach the physical limits of operation, one of the main design challenges of Systems-on-Chips (SoCs) will be to provide dynamic (run-time) support against permanent and intermittent faults that can occur in the system. ...

A system for measuring blood pressure of a user that comprises an ElectroCardioGram (ECG) circuit with at least two ECG electrodes configured to obtain an electrical activity of a heart of the user by measuring the electrical signals detected at the at lea ...

On-chip wires are becoming unreliable as the effect of various noise sources increases with technology scaling. This leads to unpredictable timing delay variations on the interconnect wires. There is a significant need to mitigate the effect of parasitics ...

Networks on Chips (NoCs) are required to tackle the increasing delay and poor scalability issues of bus-based communication architectures. Many of today’s NoC designs are based on single path routing. By utilizing multiple paths for routing, congestion in ...

As embedded computing evolves towards ever more powerful architectures, the challenge of properly interconnecting large numbers of on-chip computation blocks is becoming prominent. Networks-on-Chip (NoCs) have been proposed as a scalable solution to both p ...

It is widely recognized today that there is an alarming rise of lifestyle-induced chronic diseases (e.g., type II diabetes) in our society. Therefore, a strong need exists for cost-effective and non-invasive devices that can measure blood pressure (BP) to ...

The equivalent English title: "Design of Custom Networks-on-Chip with Physical Layout Information" Abstract translated into English: Due to the growing demand of communication between processors and memory devices in Systems-on-Chip (SoCs), recently the ne ...

Many classes of applications require Quality of Service (QoS) guarantees from the system interconnect. In Networks-on-Chip (NoC) QoS guarantees usually translate into bandwidth and latency constraints for the traffic flows and require hardware support in t ...

We consider the problem of adjusting speeds of multiple computer processors, sharing the same thermal environment, such as a chip or multichip package. We assume that the speed of each processor (and associated variables such as power supply voltage) can b ...

Networks on Chip (NoC) has been proposed as a scalable and reusable solution for interconnecting the ever- growing number of processor/memory cores on a single silicon die. As the hardware complexity of a NoC is significant, methods for designing a NoC wit ...

In this work we present a multi-path routing strategy that guarantees in-order packet delivery for Networks on Chips (NoCs). We present a design methodology that uses the routing strategy to optimally spread the traffic in the NoC to minimize the network b ...

Real-time (RT) communication support is a critical requirement for many complex embedded applications which are currently targeted to Network-on-chip (NoC) platforms. In this paper, we present novel methods to efficiently calculate worst- case bandwidth an ...

This work envisions a common design methodology, applicable for every interconnect level and based on early wire characterization, to provide a faster convergence to a feasible and robust design. We claim that such a novel design methodology is vital for u ...

Among all cardiovascular diseases, congestive heart failure (CHF) has a very high rate of hospitalization and mortality. In order to prevent hospitalization, there is a strong need to identify patients at risk of a CHF event by estimating a set of relevant ...

Many Networks-on-Chip (NoC) applications exhibit one or more critical traffic flows that require hard Quality of Service (QoS). Guaranteeing bandwidth and latency for such real time flows is crucial. In this paper, we present novel methods to efficiently c ...

Detection and classification of human emotions from multiple bio-signals has a wide variety of applications. Though electronic devices are available in the market today that acquire multiple body signals, the classification of human emotions in real-time, ...

A method for classification of ECG beats into normal and different categories of abnormal beats. The method comprises the following steps, performed on a computing platform: a. performing a training phase comprising taking as an input one or more ECG beats ...

Srinivasan Murali

Chat with Graph Search

Synthesis of Networks on Chips for 3D Systems on Chips

Networks on Chips: From Research to Products

Reliability Support for On-chip Memories Using Networks-on-Chips

Method and Device for Non-Invasive Blood Pressure Measurement

Comparison of a Timing-Error Tolerant Scheme with a Traditional Re-transmission Mechanism for Networks on Chips

A Method for Routing Packets Across Multiple Paths in NoCs with In-Order Delivery and Fault-Tolerance Guarantees

NoC Design and Implementation in 65 nm Technology

Estimation of Blood Pressure and Pulse Transit Time Using Your Smartphone

Diseño de redes en chip de propósito específico con información de rutado físico

Designing Best Effort Networks-on-Chip to Meet Hard Latency Constraints

Processor Speed Control with Thermal Constraints

Routing Aware Switch Hardware Customization for Networks on Chips

A Multi-Path Routing Strategy with Guaranteed In-order Packet Delivery and Fault Tolerance for Networks on Chips

Computing Accurate Performance Bounds for Best Effort Networks-on-Chip

Early Wire Characterization for Predictable Network-on-Chip Global Interconnects

Touch-Based System for Beat-to-Beat Impedance Cardiogram Acquisition and Hemodynamic Parameters Estimation

SunFloor 3D: A Tool for Networks on Chip Topology Synthesis for 3D Systems on Chip

A Method for Calculating Hard QoS Guarantees for Networks-on-Chip

Energy-Aware Embedded Classifier Design for Real-Time Emotion Analysis

Method for detecting abnormalities in an electrocardiogram