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David Atienza Alonso

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Publications associées (385)

NoC emulation: a tool and design flow for MPSoC

Giovanni De Micheli, Nicolas Genko, David Atienza Alonso, Luca Benini

Current Systems-On-Chip (SoC) execute applications that demand extensive parallel processing; thus, the amount of processors, memories and application-specific signal pro- cessing cores is rapidly increasing. In these new Multi- Processor SoCs, (MPSoCs) on ...

2007

Early Wire Characterization for Predictable Network-on-Chip Global Interconnects

Yusuf Leblebici, Stéphane Badel, Ilhan Hatirnaz, Giovanni De Micheli, David Atienza Alonso, Srinivasan Murali

This work envisions a common design methodology, applicable for every interconnect level and based on early wire characterization, to provide a faster convergence to a feasible and robust design. We claim that such a novel design methodology is vital for u ...

ACM Press New York, NY, US2007

A Method for Routing Packets Across Multiple Paths in NoCs with In-Order Delivery and Fault-Tolerance Guarantees

Giovanni De Micheli, David Atienza Alonso, Luca Benini, Srinivasan Murali

Networks on Chips (NoCs) are required to tackle the increasing delay and poor scalability issues of bus-based communication architectures. Many of today’s NoC designs are based on single path routing. By utilizing multiple paths for routing, congestion in ...

2007

NoC Design and Implementation in 65 nm Technology

Giovanni De Micheli, David Atienza Alonso, Federico Angiolini, Luca Benini, Srinivasan Murali

As embedded computing evolves towards ever more powerful architectures, the challenge of properly interconnecting large numbers of on-chip computation blocks is becoming prominent. Networks-on-Chip (NoCs) have been proposed as a scalable solution to both p ...

2007

Exploring Temperature-Aware Design of Memory Architectures in VLIW Systems

David Atienza Alonso, José Luis Ayala Rodrigo

This paper presents a thermal model to analyze the temperature evolution in the shared register files found on VLIW systems. The use of this model allows the analysis of several factors that have an strong impact on the heat transfer: layout topology, plac ...

IEEE Computer Society2007

Temperature-Aware Processor Frequency Assignment for MPSoCs Using Convex Optimization

Giovanni De Micheli, David Atienza Alonso, Srinivasan Murali

The increasing processing capability of Multi-Processor Systems-on-Chips (MPSoCs) is leading to an increase in chip power dissipation, which in turn leads to significant increase in chip temperature. An important challenge facing the MPSoC designers is to ...

2007

Fault-Tolerant Multi-Level Logic Decoder for Nanoscale Crossbar Memory Arrays

Didier Bouvet, Yusuf Leblebici, Mihai Adrian Ionescu, Kirsten Emilie Moselund, Giovanni De Micheli, David Atienza Alonso, Mohamed Haykel Ben Jamaa

Several technologies with sub-lithographic features are targeting the fabrication of crossbar memories in which the nanowire decoder is playing a major role. In this paper, we suggest a way to reduce the decoder size and keep it defect tolerant by using mu ...

2007

Reduction of Register File Delay Due to Process Variability in VLIW Embedded Processors

Giovanni De Micheli, David Atienza Alonso, José Luis Ayala Rodrigo

Process variation in future technologies can cause severe performance degradation since different parts of the shared Register File (RF) in VLIW processors may operate at various speeds. In this paper we present a complete approach that handles speed varia ...

2007

Application of FPGA Emulation to SoC Floorplan and Packaging Exploration

Giovanni De Micheli, David Atienza Alonso, Luca Benini, Pablo Garcia del Valle, Roman Hermida Correa

New tendencies in the consumer electronics market present Multi-Processor Systems-On-Chip (MPSoCs) as a promising solution for meeting the processing demands of upcoming generations of user applications. MPSoCs are complex to design, as they must execute m ...

2007

Multi-Processor Operating System Emulation Framework with Thermal Feedback for Systems-on-Chip

Giovanni De Micheli, David Atienza Alonso, Luca Benini, Pablo Garcia del Valle, Francisco Javier Rincon Vallejos

Multi-Processor System-On-Chip (MPSoC) can provide the performance levels required by high-end embedded applications. However, they do so at the price of an increasing power density, which may lead to thermal runaway if coupled with low-cost packaging and ...

2007

Bringing NoCs to 65nm

Giovanni De Micheli, David Atienza Alonso, Federico Angiolini, Luca Benini, Srinivasan Murali

Very deep submicron process technologies are ideal application fields for NoCs, which offer a promising solution to the scalability problem. This article sheds light on the benefits and challenges of Noc-Based interconnect design in nanometer CMOS. The aut ...

2007

Synthesis of Predictable Networks-on-Chip Based Interconnect Architectures for Chip Multi-Processors

Giovanni De Micheli, David Atienza Alonso, Luca Benini, Srinivasan Murali

Today, chip multiprocessors (CMPs) that accommodate multiple processor cores on the same chip have become a reality. As the communication complexity of such multicore systems is rapidly increasing, designing an interconnect architecture with predictable be ...

2007

Reconfiguration Strategies for Environmentally Powered Devices: Theoretical Analysis and Experimental Validation

Giovanni De Micheli, Alexandru Emilian Susu, David Atienza Alonso

Environmental energy is becoming a feasible alternative to traditional energy sources for ultra low-power devices such as sensor nodes. These devices can run reactive applications that adapt their control flow depending on the sensed data. In order to redu ...

Springer-Verlag Berling2007

Improving the Fault Tolerance of Nanometric PLA Designs

Giovanni De Micheli, David Atienza Alonso, Mohamed Haykel Ben Jamaa, Federico Angiolini, Luca Benini

Several alternative building blocks have been proposed to replace planar transistors, among which a prominent spot belongs to nanometric laments such as Silicon NanoWires (SiNWs) and Carbon NanoTubes (CNTs). However, chips leveraging these nanoscale struct ...

2007

A Multi-Path Routing Strategy with Guaranteed In-order Packet Delivery and Fault Tolerance for Networks on Chips

Giovanni De Micheli, David Atienza Alonso, Luca Benini, Srinivasan Murali

In this work we present a multi-path routing strategy that guarantees in-order packet delivery for Networks on Chips (NoCs). We present a design methodology that uses the routing strategy to optimally spread the traffic in the NoC to minimize the network b ...

2006

A Complete Multi-Processor System-on-Chip FPGA-Based Emulation Framework

Giovanni De Micheli, David Atienza Alonso, Luca Benini, Pablo Garcia del Valle

With the growing complexity in consumer embedded products and the improvements in process technology, Multi-Processor System-On-Chip (MPSoC) architectures have become widespread. These new systems are very complex to design as they must execute multiple co ...

2006

Designing Application-Specific Networks on Chips with Floorplan Information

Giovanni De Micheli, David Atienza Alonso, Federico Angiolini, Luca Benini, Srinivasan Murali

With increasing communication demands of processor and memory cores in Systems on Chips (SoCs), scalable Networks on Chips (NoCs) are needed to interconnect the cores. For the use of NoCs to be feasible in today’s industrial designs, a custom-tailored, app ...

2006

Diseño de redes en chip de propósito específico con información de rutado físico

Giovanni De Micheli, David Atienza Alonso, Federico Angiolini, Luca Benini, Srinivasan Murali, Roman Hermida Correa

The equivalent English title: "Design of Custom Networks-on-Chip with Physical Layout Information" Abstract translated into English: Due to the growing demand of communication between processors and memory devices in Systems-on-Chip (SoCs), recently the ne ...

2006

Reliability Support for On-chip Memories Using Networks-on-Chips

Giovanni De Micheli, David Atienza Alonso, Federico Angiolini, Luca Benini, Srinivasan Murali

As the geometries of the transistors reach the physical limits of operation, one of the main design challenges of Systems-on-Chips (SoCs) will be to provide dynamic (run-time) support against permanent and intermittent faults that can occur in the system. ...

2006

Comparison of a Timing-Error Tolerant Scheme with a Traditional Re-transmission Mechanism for Networks on Chips

Giovanni De Micheli, David Atienza Alonso, Federico Angiolini, Luca Benini, Srinivasan Murali

On-chip wires are becoming unreliable as the effect of various noise sources increases with technology scaling. This leads to unpredictable timing delay variations on the interconnect wires. There is a significant need to mitigate the effect of parasitics ...

2006

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