Publications de Yusuf Leblebici

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PowerPC Architecture microcontrollers are commonly used in embedded applications. In this work we present FireBird, the first PowerPC based SoC for reliable operation beyond 200C. It is a significant challenge to design SoCs for reliable operation at high ...

A micro-watt power subthreshold current modulator suitable for low-power and low-noise sensor interfaces is presented. The prototype design is based on Subthreshold Source Coupled Logic (STSCL) cells and implemented in a 0.18 μm standard CMOS technology. T ...

A new top-down design flow (RTL-to-GDSII) is proposed for achieving high-performance and noiseimmune designs consisting of differential logic blocks. The differential building blocks are based on the currentmode logic (CML), which offers true differentiali ...

This article presents a fully on-chip low-power low drop-out (LDO) voltage regulator dedicated to remotely powered wireless cortical implants. This regulator is stable over the full range of alternating current without the need of dedicated active circuitr ...

New circuit design techniques for implementing very high-valued resistors are presented, significantly improving power and area efficiency of analog front-end signal processing in ultra-low power (ULP) biomedical systems. Ranging in value from few hundreds ...

This article explores the main tradeoffs in design of subthreshold source-couple logic (STSCL) circuits. It is shown analytically that the bias current of each STSCL gate can be reduced to few pico-amperes with a reliable logic operation. Measurements on d ...

This paper presents a die-level post-CMOS processing protocol for multi-layer homogeneous 3D integration with adhesive bonding technique using parylene-C as an intermediate bonding layer and sidewall passivation material. This protocol was used to fabricat ...

A novel modular, cost e ffective 3D multi-processor architecture is presented. Auto-configurable and independently testable identical dies are stacked exploiting Through-Silicon-Vias (TSV) technology, allowing to target different market segments by selecti ...

This paper presents a regular layout fabric made of via-programmable MCML universal logic cells for structured ASIC applications and the associated design flow. The proposed structured ASIC fabric offers high speed operation, very high noise immunity, as w ...

The Field Programmable Counter Array (FPCA) was introduced to improve FPGA performance for arithmetic circuits. An FPCA is a reconfigurable IP core that can be integrated into an FPGA. To exploit the FPCA, a circuit is transformed by merging disparate addi ...

A new architecture for successive-approximation register analog-to-digital converters (SAR ADC) using generalized non-binary search algorithm is proposed to reduce the complexity and power consumption of the digital circuitry. The proposed architecture is ...

The impact of Phase Change Memory (PCM) as well as other Non-Volatile Memory (NVM) device characteristics on the quantitative classification performance of artificial neural networks is studied. Our results show that any NVM-based neural network — not just ...

A novel approach for implementing MOS current-mode logic (MCML) circuits that can operate with ultra low bias currents is introduced. Measurements of test structures fabricated in 0.18 μm CMOS technology show that the proposed PMOS load device concept can ...

Neuromorphic systems provide biologically inspired methods of computing, alternative to the classical von Neumann approach. In these systems, computation is performed by a network of spiking neurons controlled by the values of their synaptic weights, which ...

In this paper the advantages of using Differential Cascode Voltage Switch Pass Gate (DCVSPG) logic with regard to standard CMOS for subthreshold operation are presented. The two families are compared in terms of their performance and Energy-Delay-Product ( ...

We have designed and fabricated double-gate ambipolar field-effect transistors, which exhibit p-type and n-type characteristics by controlling the polarity of the second gate. In this work, we present an approach for designing an efficient regular layout, ...

This work presents an area and power efficient encoding system for wireless implantable devices capable of monitoring the electrical activity of the brain. Such devices are becoming an important tool for understanding, real-time monitoring, and potentially ...

This paper presents the design and analysis of a serial link transceiver (TRX) architecture employing analog multi-tone (AMT) signaling for chip-to-chip communication. Multi-tone single-sideband (SSB) signaling scheme is proposed in TRX architecture in ord ...

Resistive-switching random access memory (ReRAM) technologies are nowadays a good candidate to overcome the bottleneck of Von Neumann architectures, taking advantage of their logic-in-memory capability and the ability to mimic biological synapse behavior. ...

Yusuf Leblebici

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FireBird: PowerPC e200 Based SoC for High Temperature Operation

A 5.43-μW 0.8-V Subthreshold Current-Sensing Σ∆ Modulator for Low-Noise Sensor Interfaces

Towards a Unified Top-Down Design Flow for Fully-Differential Logic Blocks with Improved Speed and Noise Immunity

A Fully On-Chip LDO Voltage Regulator for Remotely Powered Cortical Implants

Power and Area Efficient MOSFET-C Filter for Very Low Frequency Applications

Pico-Watt Source-Coupled Logic Circuits

Copper TSV-Based Die-Level Via-Last 3D Integration Process with Parylene-C Adhesive Bonding Technique

Towards Cost Effective Multi-Core Processor Platforms Using 3-D Stacking Technology

Via-Programmable Structured ASIC Fabric Based on MCML Cells: Design-Flow and Implementation

Architectural improvements for field programmable counter arrays: enabling efficient synthesis of fast compressor trees on FPGAs

A 10-bit 50-MS/s Redundant SAR ADC with Split Capacitive-Array DAC

PCM for Neuromorphic Applications: Impact of Device Characteristics on Neural Network Performance

Ultra low power subthreshold current-mode logic utilizing a novel PMOS load device

Neuromorphic System with Phase-Change Synapses for Pattern Learning and Feature Extraction

Weak Inversion Performance of CMOS and DCVSPG Logic Families in Sub-300mV Range

Physical Synthesis onto Sea-of-Tiles with Double-Gate Silicon Nanowire Transistors

DCT Learning-Based Hardware Design for Neural Signal Acquisition Systems

A Simulation-Based Methodology for Evaluating the DPA-Resistance of Cryptographic Functional Units with Application to CMOS and MCML Technologies

Design and Modeling of Serial Data Transceiver Architecture by Employing Multi-Tone Single-Sideband Signaling Scheme

Analog Control of Retainable Resistance Multistates in HfO2 Resistive-Switching Random Access Memories (ReRAMs)