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Yusuf Leblebici

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Publications associées (405)

Embedded non–volatile memory study with surface potential based model

Alexandre Schmid, Yusuf Leblebici, Davide Garetto

Coupling coefficients calculation is known to be a critical issue in embedded Non-Volatile Memory (eNVM) compact modeling. In this paper we have implemented the charge balance method within the Brew’s Charge Sheet Model equation, determining the floating g ...

2009

Optimization of the Averaging Reliability Technique using Low Redundancy Factors for Nanoscale Technologies

Alexandre Schmid, Yusuf Leblebici, Milos Stanisavljevic

This paper presents a method enabling the evaluation of the averaging fault-tolerant technique, using the output probability density functions (PDFs) of unreliable units which are acquired from Monte Carlo simulations. The method has been verified by compa ...

2009

3D Architecture and Replaceable Layers for Label-Free DNA Biochips

Yusuf Leblebici, Andrea Cavallini, Yüksel Temiz, Sandro Carrara

Recent advances in bio-sensing technologies have led to design of bio-sensor arrays for rapid identification and quantification of various biological agents such as drugs, gene expressions, proteins, cholesterol, fats, etc. Various dedicated sensing arrays ...

2009

Memory Organization and Data Layout for Instruction Set Extensions with Architecturally Visible Storage

Paolo Ienne, Yusuf Leblebici, Philip Brisk, Panagiotis Athanasopoulos

Present application specific embedded systems tend to choose instruction set extensions (ISEs) based on limitations imposed by the available data bandwidth to custom functional units (CFUs). Adoption of the optimal ISE for an application would, in many cas ...

2009

A Micropower Neural Recording Amplifier with Improved Noise Efficiency Factor

Alexandre Schmid, Yusuf Leblebici, Vahid Majidzadeh Bafar

This article presents a neural recording amplifier suitable for large-scale integration with multi-electrode arrays (MEAs) in very low-power microelectronic cortical implants. The proposed amplifier is the most energy-efficient structure reported to date, ...

2009

A Slew Controlled LVDS Output Driver Circuit in 0.18um CMOS Technology

Yusuf Leblebici, Seyed Armin Tajalli

This article presents a power-efficient low-voltage differential signaling (LVDS) output driver circuit. The proposed approach helps to reduce the total input capacitance of the LVDS driver circuit and hence relaxes the tradeoffs in designing a low-power p ...

2009

Energy Dissipation Reduction of a Cardiac Event Detector in the Sub-Vt Domain By Architectural Folding

Yusuf Leblebici, Omer Can Akgun

This manuscript presents the digital hardware realization of a wavelet based event detector for cardiac pacemaker applications. The architecture of the detector is partially folded to minimize hardware cost. An energy model is applied to evaluate the energ ...

2009

Complete Nanowire Crossbar Framework Optimized for the Multi-Spacer Patterning Technique

Yusuf Leblebici, Giovanni De Micheli, Mohamed Haykel Ben Jamaa

Nanowire crossbar circuits are an emerging architectural paradigm that promises a higher integration density and an improved fault-tolerance due to its reconfigurability. In this paper, we propose for the first time the utilization of the multi-spacer patt ...

2009

A Fully On-Chip LDO Voltage Regulator for Remotely Powered Cortical Implants

Alexandre Schmid, Yusuf Leblebici, Vahid Majidzadeh Bafar

This article presents a fully on-chip low-power low drop-out (LDO) voltage regulator dedicated to remotely powered wireless cortical implants. This regulator is stable over the full range of alternating current without the need of dedicated active circuitr ...

2009

Decoding Nanowire Arrays Fabricated with the Multi-Spacer Patterning Technique

Yusuf Leblebici, Giovanni De Micheli, Mohamed Haykel Ben Jamaa

Silicon nanowires are a promising solution to address the increasing challenges of fabrication and design at the future nodes of the Complementary Metal-Oxide-Semiconductor (CMOS) Technology roadmap. Despite the attractive opportunity that offers their org ...

IEEE Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, NJ 08855-1331 Usa2009

Subthreshold SCL for Ultra-Low-Power SRAM and Low-Activity-Rate Digital Systems

Yusuf Leblebici, Seyed Armin Tajalli

The power efficiency of source-coupled logic (SCL) topology for implementing ultra-low-power and low-activity-rate circuits is investigated. It is shown that in low-activity-rate circuits, where the subthreshold leakage consumption of conventional CMOS cir ...

2009

Matrice de micro électrodes à haute résolution spatiale pour la mesure du potentiel extracellulaire des cellules nerveuses

Alexandre Schmid, Yusuf Leblebici, Neil Joye

Une nouvelle approche basée sur des électrodes en 3D a été développée afin d’accroître le couplage électrique entre les cellules nerveuses et les capteurs d’une matrice de micro électrodes (MEA). Cette amélioration du couplage électrique obtenue par des ma ...

2009

Electrical modeling of the cell-electrode interface for recording neural activity from high-density microelectrode arrays

Alexandre Schmid, Yusuf Leblebici, Neil Joye

Accurate electrical models are needed to support the design of modern microelectrode arrays. The point-contact model is presented thoroughly, and an area-contact model is analytically derived in order to model the electrical characteristics of the cell-ele ...

2009

Fault-Tolerance and Reliability of Post-CMOS Systems: a Circuit Perspective

Alexandre Schmid, Yusuf Leblebici, Milos Stanisavljevic

The reliability of systems made of unreliable nanoelectronic devices is discussed in this paper. Massive defect density which may affect future fabrication technologies calls for novel solutions, where spatial redundancy and the voting scheme play a signif ...

IEEE Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa2009

Semiconductor based high resistance

Yusuf Leblebici

The field of invention is in the area of MOS integrated circuits operating with very low currents in the weak inversion region or sub threshold. The method aims at providing linear resistor with a value in the multi-mega ohm range. In order to produce Sili ...

2008

A 1.8V 12-bit 230-MS/s pipeline ADC in 0.18um CMOS technology

Yusuf Leblebici, Thomas Liechti, Zeynep Toprak Deniz, Seyed Armin Tajalli, Omer Can Akgun

This paper describes the implementation of a 12-bit 230 MS/s pipelined ADC using a conventional 1.8V, 0.18μm digital CMOS process. Two-stage folded cascode OTA topology is used for improved settling performance. Extreme low-skew (less than 3ps peak-to-peak ...

IEEE2008

Fault-tolerant architectures for nanoelectronic circuits employing simple feed-forward neural networks without learning

Alexandre Schmid, Yusuf Leblebici

2008

A Generic Standard Cell Design Methodology for Differential Circuit Styles

Yusuf Leblebici, Stéphane Badel, Anna Peña Martinez, Paolo Vietti, Özgür Inaç, Erdem Güleyüpoglu

2008

Pico-Watt Source-Coupled Logic Circuits

Yusuf Leblebici, Seyed Armin Tajalli

This article explores the main tradeoffs in design of subthreshold source-couple logic (STSCL) circuits. It is shown analytically that the bias current of each STSCL gate can be reduced to few pico-amperes with a reliable logic operation. Measurements on d ...

2008

Circuit Techniques to Reduce the Supply Voltage Limit of Subthreshold MCML Circuits

Yusuf Leblebici

2008

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