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Publications associées (158)

Design and Realization of a Fault-Tolerant 90nm Cryptographic Engine Capable of Performing under Massive Defect Density

Alexandre Schmid, Yusuf Leblebici, Milos Stanisavljevic, Maria Gabrani

This paper presents a new approach for assessing the reliability of nanometer-scale devices prior to fabrication and a practical reliability architecture realization. A four-layer architecture exhibiting a large immunity to permanent as well as random fail ...

ACM2007

Three-dimensional Tip Electrode Array Technology for High Resolution Neuro-Electronic Systems used in Electrophysiological Experiments in-vitro

Alexandre Schmid, Yusuf Leblebici, Neil Joye, Maurizio Lavagnino

A three-dimensional tip electrode array technology for in-vitro electrophysiological experiments is presented. Based on simulation results obtained with a finite element model of the neuron-electrode interface, it has been shown that the electrical couplin ...

2007

Toward a bio-inspired image processor for edge extraction with single-electron devices

Alexandre Schmid, Yusuf Leblebici

2007

Case Study of Fault-Tolerant Architectures for 90nm CMOS Cryptographic Cores

Alexandre Schmid, Yusuf Leblebici, Milos Stanisavljevic, Maria Gabrani

This paper presents a case study of different fault-tolerant architectures. The emphasis is on the silicon realization. A 128bit AES cryptographic core has been designed and fabricated as a main topology on which the fault-tolerant architectures have been ...

2007

Fault Tolerance of Feed-Forward Artificial Neural Network Architectures Targeting Nano-Scale Implementations

Alexandre Schmid, Yusuf Leblebici, Ayfer Özgür Aydin, Mehmet Vural

2007

A 90nm CMOS Cryptographic Core with Improved Fault- Tolerance in Presence of Massive Defect Density

Alexandre Schmid, Yusuf Leblebici, Milos Stanisavljevic

2007

Fault-Tolerance of Robust Feed-Forward Architecture Using Single-Ended and Differential Deep-Submicron Circuits Under Massive Defect Density

Alexandre Schmid, Yusuf Leblebici, Milos Stanisavljevic

An assessment of the fault-tolerance properties of single-ended and differential signaling is shown in the context of a high defect density environment, using a robust error-absorbing circuit architecture. A software tool based on Monte-Carlo simulations i ...

IEEE2006

Charge-Based CMOS Realization of Unconventional Functions

Alexandre Schmid, Yusuf Leblebici

2006

CONAN - A Design Exploration Framework for Reliable Nano-Electronics Architectures

Alexandre Schmid, Yusuf Leblebici, Mihai Adrian Ionescu

2005

Nanowire for Room Temperature Operated Hybrid CMOS-‘NANO’ Integrated Circuits

Michel Declercq, Serge Ecoffey, Alexandre Schmid, Yusuf Leblebici, Vincent Pott, Mihai Adrian Ionescu, Marco Mazza

2005

Precisely-timed synchronization among spiking neuron circuits on silicon neural networks - Analog implementation of integrate-and-fire neurons, depressing synapses, and STDP learning units

Alexandre Schmid, Yusuf Leblebici

2005

New Logic Family Based on Hybrid MOSFET-Polysilicon Nano-Wires

Didier Bouvet, Michel Declercq, Serge Ecoffey, Alexandre Schmid, Yusuf Leblebici, Vincent Pott, Mihai Adrian Ionescu, Marco Mazza

2005

A Methodology for Reliability Enhancement of Nanometer-Scale Digital Systems Based on A-Priori Functional Fault-Tolerance Analysis

Alexandre Schmid, Yusuf Leblebici, Vineet Abhishek, Milos Stanisavljevic

This paper presents a new approach for monitoring and estimating device reliability of nanometer-scale devices prior to fabrication. A four-layer architecture exhibiting a large immunity to permanent as well as random failures is used. A complete tool for ...

IFIP2005

VLSI realization of mixed analog-digital artificial neural networks dedicated to autonomous systems with on-chip learning capability

Alexandre Schmid

EPFL2000

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Alexandre Schmid

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Design and Realization of a Fault-Tolerant 90nm Cryptographic Engine Capable of Performing under Massive Defect Density

Three-dimensional Tip Electrode Array Technology for High Resolution Neuro-Electronic Systems used in Electrophysiological Experiments in-vitro

Toward a bio-inspired image processor for edge extraction with single-electron devices

Case Study of Fault-Tolerant Architectures for 90nm CMOS Cryptographic Cores

Fault Tolerance of Feed-Forward Artificial Neural Network Architectures Targeting Nano-Scale Implementations

A 90nm CMOS Cryptographic Core with Improved Fault- Tolerance in Presence of Massive Defect Density

Fault-Tolerance of Robust Feed-Forward Architecture Using Single-Ended and Differential Deep-Submicron Circuits Under Massive Defect Density

Charge-Based CMOS Realization of Unconventional Functions

CONAN - A Design Exploration Framework for Reliable Nano-Electronics Architectures

Nanowire for Room Temperature Operated Hybrid CMOS-‘NANO’ Integrated Circuits

Precisely-timed synchronization among spiking neuron circuits on silicon neural networks - Analog implementation of integrate-and-fire neurons, depressing synapses, and STDP learning units

New Logic Family Based on Hybrid MOSFET-Polysilicon Nano-Wires

A Methodology for Reliability Enhancement of Nanometer-Scale Digital Systems Based on A-Priori Functional Fault-Tolerance Analysis

Fault-Tolerant Logic Gates with Neuromorphic CMOS Circuits

On the Fault-Tolerance of a Clustered Single-Electron Neural Network for Differential Enhancement

Single-Electron Circuit for Inhibitory Spiking Neural Network with Fault-Tolerant Architecture

Analysis of Reliability in Nano-Scale Circuits and Systems Based on A-Priori Statistical Fault-Modeling Methodology

VLSI realization of mixed analog-digital artificial neural networks dedicated to autonomous systems with on-chip learning capability