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Concept

Zero ASIC

Publications associées (27)

Automating the Design of Programmable Interconnect for Reconfigurable Architectures

Stefan Nikolic

With Moore's law coming to an end, increasingly more hope is being put in specialized hardware implemented on reconfigurable architectures such as Field-Programmable Gate Arrays (FPGAs). Yet, it is often neglected that these architectures themselves experi ...

EPFL2023

HetCache: Synergising NVMe Storage and GPU acceleration for Memory-Efficient Analytics

Anastasia Ailamaki, Periklis Chrysogelos, Syed Mohammad Aunn Raza, Hamish Mcniece Hill Nicholson

Accessing input data is a critical operation in data analytics: i) slow data access significantly degrades performance, and ii) storing everything in the fastest medium, i.e., memory, incurs high operational and hardware costs. Further, while GPUs offer in ...

2023

Analysis of Functional Errors Produced by Long-Term Workload-Dependent BTI Degradation in Ultra-Low Power Processors

David Atienza Alonso, Alexandre Sébastien Julien Levisse, Miguel Peon Quiros, Ruben Braojos Lopez, Loris Gérard Duch

Aging effects in digital circuits change the switching characteristics of their transistors, resulting in timing violations that can lead to functional errors at the system level. In particular, BTI is a degradation effect that changes the threshold voltag ...

2020

Snap-On User-Space Manager for Dynamically Reconfigurable System-on-Chips

Paolo Ienne, Andrea Guerrieri, Sahand Kashani

Due to increased embedded processing requirements, modern SoCs are becoming heterogeneous computing platforms by combining traditional processing units with custom reconfigurable hardware accelerators (HAs) on an FPGA fabric. However, efficiently managing ...

2019

Rethinking Secure FPGAs: Towards a Cryptography-friendly Configurable Cell Architecture and its Automated Design Flow

Edoardo Charbon, Francesco Regazzoni

This work proposes the first fine-grained configurable cell array specifically tailored for the implementation of cryptographic algorithms that can be configured using widely adopted hardware description languages. Our solution can be added as a small, cry ...

IEEE2018

Performance characterization of Altera and Xilinx 28 nm FPGAs at cryogenic temperatures

Edoardo Charbon

Quantum computers enable a massive speed-up in calculations, thanks to the nature of quantum operations. To unlock quantum computation, a classical system infrastructure is required for the control of qubits and processing of their data. While qubits are g ...

2018

Abstracting Multi-Core Topologies with MCTOP

Rachid Guerraoui, Vasileios Trigonakis, Georgios Chatzopoulos

Portability and efficiency are usually antagonists in multi-core computing. In order to develop efficient code, one needs to take into account the topology of the target multi-cores (e.g., for locality). This clearly hampers code portability. In this paper ...

ACM Press2017

High-Precision Performance Estimation of Dynamic Dataflow Programs

Marco Mattavelli, Simone Casale Brunet, Endri Bezati, Malgorzata Maria Michalska

An important challenge for a dataflow designer is to efficiently explore the design space in order to find a set of configurations that satisfy the defined objective function. The exploration directions may involve the partitioning, scheduling and buffer d ...

2016

Design Space Exploration Problem Formulation for Dataflow Programs on Heterogeneous Architectures

Marco Mattavelli, Endri Bezati, Nicolas Zufferey, Malgorzata Maria Michalska

The implementations of signal processing systems on the emerging many-core or multi-core processing platforms require to solve a very difficult problem: how to partition and schedule the processing tasks according to given optimization functions such as da ...

2016

Programming Models and Methods for Heterogeneous Parallel Embedded Systems

Marco Mattavelli, Simone Casale Brunet, Endri Bezati

The growing complexity of digital signal processing applications makes a compelling case for the adoption of higher-level programming models such as dataflow for the implementation of applications on programmable logic devices and many/multi-core embedded ...

2016

Sub-electron CIS noise analysis in 65 nm process

Christian Enz, Assim Boukhayma, Raffaele Capoccia

For a 4T pixel-based CMOS image sensors (CIS) readout chain, with column-level amplification and CDS, we show that the input-referred total noise in a standard 65 nm process can be reduced to 0.37 e-rms. Based on transient noise simulation using Eldo, the ...

2016

Design and Measurement Methodology for a Sub-picoampere Current Digitiser

Maher Kayal, François Krummenacher, Evgenia Voulgari

This paper introduces some design and measurement techniques that were used in the design and the testing of an ASIC for ultra-low current sensing. The idea behind this paper is to present the limitations in sub-picoampere current measurements and demonstr ...

Ieee2015

GPU Acceleration for Simulating Massively Parallel Many-Core Platforms

David Atienza Alonso, Luca Benini, Martino Ruggiero, Shivani Raghav

Emerging massively parallel architectures such as a general-purpose processor plus many-core programmable accelerators are creating an increasing demand for novel methods to perform their architectural simulation. Most state-of-the-art simulation technolog ...

Institute of Electrical and Electronics Engineers2015

Dataflow Programs Analysis and Optimization Using Model Predictive Control Techniques. Two Examples of Bounded Buffer Scheduling: Deadlock Avoidance and Deadlock Recovery Strategies

Marco Mattavelli, Endri Bezati, Simone Casale Brunet

The analysis of the trace graphs generated by dataflow program executions has been shown to be an effective tool for exploring and optimizing the design space of application programs on manycore/multicore platforms. In this work a new approach aiming at fi ...

Springer2015

Efficient Communication and Synchronization on Manycore Processors

Darko Petrovic

The increased number of cores integrated on a chip has brought about a number of challenges. Concerns about the scalability of cache coherence protocols have urged both researchers and practitioners to explore alternative programming models, where cache co ...

EPFL2015

A Miniaturized Insect Eye Inspired Multi-camera Real-time Panoramic Imaging System

Ömer Cogal

During the last 50 years miniaturization became a key element in human history, since it opens doors for manufacturing new devices that enhances the quality of human life. Camera and imaging systems are following this miniaturization trend as well. Meanwhi ...

EPFL2015

Signaling in 3-D integrated circuits, benefits and challenges

Somayyeh Rahimian Omam

Three-dimensional (3-D) or vertical integration is a design and packaging paradigm that can mitigate many of the increasing challenges related to the design of modern integrated systems. 3-D circuits have recently been at the spotlight, since these circuit ...

EPFL2015

Integrated Electronics to Control and Readout Electrochemical Biosensors for Implantable Applications

Seyedeh Sara Ghoreishizadeh

Biosensors can effectively be used to monitor multiple metabolites such as glucose, lactate, ATP and drugs in the human body. Continuous monitoring of these metabolites is essential for patients with chronic or critical conditions. Moreover, this can be us ...

EPFL2015

High-Throughput Maps on Message-Passing Manycore Architectures: Partitioning versus Replication

André Schiper, Thomas Ropars, Omid Shahmirzadi

The advent of manycore architectures raises new scalability challenges for concurrent applications. Implementing scalable data structures is one of them. Several manycore architectures provide hardware message passing as a means to efficiently exchange dat ...

2014

Leveraging Hardware Message Passing for Efficient Thread Synchronization

André Schiper, Thomas Ropars, Darko Petrovic

As the level of parallelism in manycore processors keeps increasing, providing efficient mechanisms for thread synchronization in concurrent programs is becoming a major concern. On cache-coherent shared-memory processors, synchronization efficiency is ult ...

2014