The growing demand for real-time machine learning has accelerated the adoption of edge computing, which processes data locally to reduce latency, enhance privacy, and improve energy efficiency. Ultra-low-power edge applications (TinyAI) face stringent constraints in performance, power, and area, often operating within milliwatt budgets and on millimeter-scale system-on-chips (SoCs). Prototyping such systems requires hardware/software co-design platforms capable of real-time execution and accurate performance and energy measurements.
To overcome these challenges, I developed the FPGA EMUlation (FEMU), an open-source and configurable RISC-V framework for prototyping and evaluating TinyAI applications on SoC-based FPGAs. This approach combines a heterogeneous system implemented in reconfigurable logic with a software environment running on an application-class processor under a standard operating system. Virtualized I/O enables flexible communication, signal processing, and verification. Custom accelerators can be added as software models or register transfer level (RTL) modules, while silicon-derived models provide performance and energy estimations.
At the core of FEMU lies a heterogeneous system that combines a flexible host to run control and communication tasks with specialized accelerators tailored to specific application domains. However, each accelerator presents unique requirements in terms of ports, bandwidth, performance, area, and power trade-offs. As a result, a highly configurable host is essential to adapt both hardware and software to the diverse needs of these accelerators.
To address these limitations, I designed the eXtendible Heterogeneous Energy Efficient Platform (X-HEEP), an open-source and configurable RISC-V platform that integrates seamlessly within FEMU to support the connection of TinyAI accelerators. X-HEEP provides configurable central processing units (CPUs), memory, interconnects, and peripherals, while its eXtendible Accelerator InterFace (XAIF) enables the integration of accelerators with a wide range of requirements. The platform supports FPGA prototyping, ASIC implementation, and mixed SystemC/RTL simulation, streamlining design space exploration and optimization.
While most accelerators target domain-specific tasks, more versatile solutions are required for addressing a broader range of applications with varying demands. In this context, graphics processing units (GPUs) have proven particularly effective in exploiting data parallelism across diverse workloads. When integrated with a host like X-HEEP, GPUs form accelerated processing units (APUs), creating unified systems capable of efficiently handling both control-oriented and compute-intensive tasks.
To explore this direction, I developed the embedded GPU (e-GPU), an open-source and configurable RISC-V platform that integrates within X-HEEP to investigate the feasibility and trade-offs of leveraging GPUs in the TinyAI domain. Its extensive configurability
