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Concept

Langage machine

Publications associées (22)

Instruction-Level Power Side-Channel Leakage Evaluation of Soft-Core CPUs on Shared FPGAs

Mathias Josef Payer, Mirjana Stojilovic, Ognjen Glamocanin, Shashwat Shrivastava

Side-channel disassembly attacks recover CPU instructions from power or electromagnetic side-channel traces measured during code execution. These attacks typically rely on physical access, proximity to the victim device, and high sampling rate measuring in ...

2023

Resource Sharing in Dataflow Circuits

Paolo Ienne, Andrea Guerrieri, Lana Josipovic, Axel Marmet

To achieve resource-efficient hardware designs, high-level synthesis (HLS) tools share (i.e., time-multiplex) functional units among operations of the same type. This optimization is typically performed in conjunction with operation scheduling to ensure th ...

Assoc Computing Machinery2023

Overcoming decision paralysis—A digital twin for decision making in energy system design

François Maréchal, Julia Granacher, Tuong-Van Nguyen

The design of efficient energy systems, through the development of new technologies and the improvement of current ones, requires the use of rigorous process synthesis methods for generating and analysing design alternatives. We introduce a digital twin of ...

2022

Resource Sharing in Dataflow Circuits

Paolo Ienne, Andrea Guerrieri, Lana Josipovic, Axel Marmet

To achieve resource-efficient hardware designs, HLS tools share (i.e., time-multiplex) functional units among operations of the same type. This optimization is typically performed together with operation scheduling to ensure the best possible unit usage at ...

IEEE2022

Too Quiet in the Library: An Empirical Study of Security Updates in Android Apps' Native Code

Mathias Josef Payer

Android apps include third-party native libraries to increase performance and to reuse functionality. Native code is directly executed from apps through the Java Native Interface or the Android Native Development Kit. Android developers add precompiled nat ...

IEEE COMPUTER SOC2021

SpecROP: Speculative Exploitation of ROP Chains

Mathias Josef Payer, Atri Bhattacharyya, Andrés Sánchez Marín

Speculative execution attacks, such as Spectre, reuse code from the victim’s binary to access and leak secret information during speculative execution. Every variant of the attack requires very particular code sequences, necessitating elaborate gadget-sear ...

2020

Block Oriented Programming: Automating Data-Only Attacks

Mathias Josef Payer

With the widespread deployment of Control-Flow Integrity (CFI), control-flow hijacking attacks, and consequently code reuse attacks, are significantly more difficult. CFI limits control flow to well-known locations, severely restricting arbitrary code exec ...

ASSOC COMPUTING MACHINERY2018

Automatic Generation of Efficient Accelerators for Reconfigurable Hardware

Christos Kozyrakis

Acceleration in the form of customized datapaths offer large performance and energy improvements over general purpose processors. Reconfigurable fabrics such as FPGAs are gaining popularity for use in implementing application-specific accelerators, thereby ...

Ieee2016

Interactive Synthesis using Free-Form Queries

Viktor Kuncak, Tihomir Gvero

We present a new code assistance tool for integrated development environments. Our system accepts free-form queries allowing a mixture of English and Java as an input, and produces Java code fragments that take the query into account and respect syntax, ty ...

2015

Representation of Medical Guidelines with a Computer Interpretable Model

Giovanni De Micheli, Alena Simalatsar, Wenqi You Dubout

Nowadays medical software is tightly coupled with medical devices that perform patient state monitoring and lately even some basic treatment procedures. Medical guidelines (GLs) can be seen as specification of a medical system which requires their computer ...

World Scientific Publ Co Pte Ltd2014

Alternating Control Flow Reconstruction

Johannes Kinder

Unresolved indirect branch instructions are a major obstacle for statically reconstructing a control flow graph (CFG) from machine code. If static analysis cannot compute a precise set of possible targets for a branch, the necessary conservative over-appro ...

Springer2012

Towards Static Analysis of Virtualization-Obfuscated Binaries

Johannes Kinder

Virtualization-obfuscation protects a program from manual or automated analysis by compiling it into bytecode for a randomized virtual architecture and attaching a corresponding interpreter. Static analysis appears to be helpless on such programs, where on ...

IEEE2012

Instruction Set Extensions for Cryptographic Hash Functions on a Microcontroller Architecture

Andreas Peter Burg, Jeremy Hugues-Felix Constantin

In this paper, we investigate the benefits of instruction set extensions (ISEs) on a 16-bit microcontroller architecture for software implementations of cryptographic hash functions, using the example of the five SHA-3 final round candidates. We identify t ...

Ieee2012

Language Virtualization for Heterogeneous Parallel Computing

Martin Odersky, Tiark Rompf

As heterogeneous parallel systems become dominant, application developers are being forced to turn to an incompatible mix of low level programming models (e.g. OpenMP, MPI, CUDA, OpenCL). However, these models do little to shield developers from the diffic ...

2010

Iterative geometric design for architecture

This work investigates on computer aided integrated architectural design and production. The aim is to provide integral solutions for the design and the production of geometrically complex free-form architecture. Investigations on computer aided geometric ...

EPFL2009

Advanced Java Bytecode Instrumentation

Bytecode instrumentation is a valuable technique for transparently enhancing virtual execution environments for purposes such as monitoring or profiling. Current approaches to bytecode instrumentation either exclude some methods from instrumentation, sever ...

2007

Reengineering Standard Java Runtime Systems through Dynamic Bytecode Instrumentation

Java bytecode instrumentation is a widely used technique, especially for profiling purposes. In order to ensure the instrumentation of all classes in the system, including dynamically generated or downloaded code, instrumentation has to be performed at run ...

2007

A Quantitative Evaluation of the Contribution of Native Code to Java Workloads

Many performance analysis tools for Java focus on tracking executed bytecodes, but provide little support in determining the specific contribution of native code libraries. This paper introduces and assesses a portable approach for characterizing the amoun ...

2006

Exact and Portable Profiling for the JVM Using Bytecode Instruction Counting

This paper presents a novel profiling approach, which is entirely based on program transformation techniques in order to enable exact profiling, preserving complete call stacks, method invocation counters, and bytecode instruction counters. We exploit the ...

2006

Improving instruction cache performance in OLTP

Anastasia Ailamaki

Instruction-cache misses account for up to 40%; of execution time in online transaction processing (OLTP) database workloads. In contrast to data cache misses, instruction misses cannot be overlapped with out-of-order execution. Chip design limitations do ...

Association for Computing Machinery2006

Publications associées (22)