Publications associées à Motorola 6800

Low-Power Artificial Neural Network Perceptron Based on Monolayer MoS2

Aleksandra Radenovic, Andras Kis, Zhenyu Wang, Mukesh Kumar Tripathi, Guilherme Migliato Marega

Machine learning and signal processing on the edge are poised to influence our everyday lives with devices that will learn and infer from data generated by smart sensors and other devices for the Internet of Things. The next leap toward ubiquitous electron ...

2022

Wafer-scale MoS2 with water-vapor assisted showerhead MOCVD

Aleksandra Radenovic, Andras Kis, Michal Daniel Macha, Yanfei Zhao, Mukesh Kumar Tripathi, Mukeshchand Thakur, Jing Zhang, Hyungoo Ji

Among numerous thin film synthesis methods, metalorganic chemical vapor deposition performed in a showerhead reactor is the most promising one for broad use in scalable and commercially adaptable two-dimensional material synthesis processes. Adapting the m ...

ROYAL SOC CHEMISTRY2022

Macro-to-Microchannel Transition in Two-Phase Flow and Evaporation

Chin Lee Ong

Continuous development of highly efficient and compact cooling elements are driven by extensive developments of Micro-Electro-Mechanical Systems (MEMS) devices such as microprocessors or micro high-powered laser systems. As microprocessors continue to head ...

EPFL2010

Hysteretic inverter-on-a-body-tied-wire based on less-than-10mV/decade abrupt punch-through impact ionization MOS (PIMOS) switch

Mihai Adrian Ionescu, Didier Bouvet, Kirsten Emilie Moselund, Vincent Pott

This work reports for the first time on a cascadable NMOS inverter based on punch-through impact ionization MOSFET (PIMOS) integrated on a single body-tied silicon wire. The PIMOS device acts as a single-transistor-latch and shows abrupt current switching ...

2008

Ultra low power subthreshold current-mode logic utilizing a novel PMOS load device

Yusuf Leblebici, Seyed Armin Tajalli, Eric Vittoz

A novel approach for implementing MOS current-mode logic (MCML) circuits that can operate with ultra low bias currents is introduced. Measurements of test structures fabricated in 0.18 μm CMOS technology show that the proposed PMOS load device concept can ...

2007

A hybrid CMOS-SET co-fabrication platform using nano-grain polysilicon wires

Mihai Adrian Ionescu, Didier Bouvet, Vincent Pott, Santanu Mahapatra, Serge Ecoffey

This paper presents a process for the co-fabrication of self-aligned NMOS and single electron transistors made by gated polysilicon wires. The realization of SET–MOS hybrid architectures is also reported. The proposed process exploits an original low energ ...

2005