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Publications associées (30)

On the Dynamic Performance of Laterally Gated Transistors

Elison de Nazareth Matioli, Armin Jafari, Mohammad Samizadeh Nikooytabalvandani, Catherine Erine, Giovanni Santoruvo

Laterally gated transistors have been proposed as an innovative device architecture in which a semiconducting channel is controlled by side gates. In this sense, the gate can either be in contact with the sidewalls or be separated by a gap. In the latter c ...

Institute of Electrical and Electronics Engineers2019

Design of approximate and precision-scalable circuits for embedded multimedia and neural-network processing

Vincent Frédéric Camus

Density, speed and energy efficiency of integrated circuits have been increasing exponentially for the last four decades following Moore's law. However, power and reliability pose several challenges to the future of technology scaling. Approximate computin ...

EPFL2019

Exploration of Negative Capacitance Devices and Technologies

Ali Saeidi

Conventional device scaling has been the main guiding principle of the MOS device engineering over these past years. However, this aggressive scaling would be eventually limited due to the inability to remove the heat generated by MOSFET devices. The power ...

EPFL2019

Improvements to Boolean resynthesis

Giovanni De Micheli, Mathias Soeken, Luca Gaetano Amarù

In electronic design automation Boolean resynthesis techniques are increasingly used to improve the quality of results where algebraic methods hit local minima Boolean methods rely on complete functional properties of a logic circuit, preferably including ...

IEEE2018

Doping-Free Complementary Logic Gates Enabled by Two-Dimensional Polarity-Controllable Transistors

Giovanni De Micheli, Giovanni Vincenzo Resta, Pierre-Emmanuel Julien Marc Gaillardon

Atomically thin two-dimensional (2D) materials belonging to transition metal dichalcogenides, due to their physical and electrical properties, are an exceptional vector for the exploration of next-generation semiconductor devices. Among them, due to the po ...

2018

Progress in single-photon avalanche diode image sensors in standard CMOS: From two-dimensional monolithic to three-dimensional-stacked technology

Edoardo Charbon, Myung Jae Lee

Single-photon detection and photon counting are useful tools in many fields, from light detection and ranging (LiDAR) to biomedical imaging and from time-resolved Raman spectroscopy to quantum applications. In this context, recently, single-photon avalanch ...

IOP PUBLISHING LTD2018

The Cryogenic Temperature Behavior of Bipolar, MOS, and DTMOS Transistors in Standard CMOS

Edoardo Charbon

Both CMOS bandgap voltage references and temperature sensors rely on the temperature behavior of either CMOS substrate BJTs or MOS transistors in weak inversion. Bipolar transistors are generally preferred over MOS transistors because of their lower spread ...

2018

Dynamical Behavior and Stability Analysis of Hydromechanical Gates

Paolo Perona, Fabian Alexander Bernhard

This study revisits the stability of hydromechanical gates for upstream water surface regulation, also known as AMIL gates. AMIL gates are used in irrigation canals, where they are often installed in series. From the regulation perspective, instabilities a ...

American Society of Civil Engineers2017

Inverter Propagation and Fan-Out Constraints for Beyond-CMOS Majority-Based Technologies

Giovanni De Micheli, Mathias Soeken, Eleonora Testa

Traditional logic synthesis faces challenges of meeting the requirements demanded by the many emerging nanotech-nologies that are based on logic models different from standard CMOS. Several emerging nanodevices including Quantum-dot Cellular Automata (QCA) ...

IEEE2017

Negative Capacitance Field Effect Transistors; Capacitance Matching and non-Hysteretic Operation

Mihai Adrian Ionescu, Christian Enz, Farzan Jazaeri, Igor Stolichnov, Ali Saeidi, Francesco Bellando

This work experimentally demonstrates negative capacitance MOSFETs in hysteretic and non-hysteretic modes of operation. A PZT capacitor is externally connected to the gate of commercial nMOSFETs fabricated in 28nm CMOS technology to explore the negative ca ...

IEEE2017