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Concept

Processeur 64 bits

Publications associées (30)

A high sensitivity low-power capacitive front-end for insulin injection pens

Maher Kayal, François Krummenacher, Jean-Baptiste Robert Orhan, François Pierre Gaugaz

A low-power 14-bits first order incremental Analog-to-Digital Converter (ADC) is presented. Based on the charge balancing principle, this switched-capacitor (SC) circuit integrates the input signal multiple times to reach the targeted resolution, linearity ...

ELSEVIER SCI LTD2019

Bits through Time

Elie Najm

In any communication system, there exist two dimensions through which the information at the source becomes distorted before reaching the destination: the noisy channel and time. Messages transmitted through a noisy channel are susceptible to modification ...

EPFL2019

RRAM Crossbar Arrays for Storage Class Memory Applications : Throughput and Density Considerations

Alexandre Sébastien Julien Levisse

As more and more high density memories are required to satisfy the Internet of Things ecosystem, academics and industrials are looking for an intermediate solution to fill the gap between DRAM and Flash NAND in the memory hierarchy. The emergence of Resist ...

2018

Massively parallel data processing for quantitative total flow imaging with optical coherence microscopy and tomography

Theo Lasser, Daniel Pawel Szlag, Paul James Marchand, Marcin Antoni Sylwestrzak

We present an application of massively parallel processing of quantitative flow measurements data acquired using spectral optical coherence microscopy (SOCM). The need for massive signal processing of these particular datasets has been a major hurdle for m ...

Elsevier2017

A Steep-Slope Transistor Combining Phase-Change and Band-to-Band-Tunneling to Achieve a sub-Unity Body Factor

Mihai Adrian Ionescu, Josef Andreas Schuler, Wolfgang Amadeus Vitale, Anna Krammer, Emanuele Andrea Casu, Arnab Biswas, Cem Alper, Teodor Rosca

Steep-slope transistors allow to scale down the supply voltage and the energy per computed bit of information as compared to conventional field-effect transistors (FETs), due to their sub-60 mV/decade subthreshold swing at room temperature. Currently pursu ...

Nature Research2017

Some Cryptanalytic Results on Lizard

Subhadeep Banik

Lizard is a lightweight stream cipher proposed by Hamann, Krause and Meier in IACR ToSC 2017. It has a Grain-like structure with two state registers of size 90 and 31 bits. The cipher uses a 120 bit secret key and a 64 bit IV. The authors claim that Lizard ...

2017

A reconfigurable cryogenic platform for the classical control of quantum processors

Edoardo Charbon

The implementation of a classical control infrastructure for large-scale quantum computers is challenging due to the need for integration and processing time, which is constrained by coherence time. We propose a cryogenic reconfigurable platform as the hea ...

2017

FloDB: Unlocking Memory in Persistent Key-Value Stores

Rachid Guerraoui, Mihail Igor Zablotchi, Vasileios Trigonakis, Oana Maria Balmau

Log-structured merge (LSM) data stores enable to store and process large volumes of data while maintaining good performance. They mitigate the I/O bottleneck by absorbing updates in a memory layer and transferring them to the disk layer in sequential batch ...

2017

Near-Memory Address Translation

Babak Falsafi, Javier Picorel Obando, Dorde Jevdic

Memory and logic integration on the same chip is becoming increasingly cost effective, creating the opportunity to offload data-intensive functionality to processing units placed inside memory chips. The introduction of memory-side processing units (MPUs) ...

Ieee2017

DynOR: A 32-bit Microprocessor in 28 nm FD-SOI with Cycle-By-Cycle Dynamic Clock Adjustment

Andreas Peter Burg, Andrea Bonetti, Adam Shmuel Teman, Jeremy Hugues-Felix Constantin, Thomas Christoph Müller, Lorenz Flavio Schmid

This paper presents DynOR, a 32-bit 6-stage OpenRISC microprocessor with dynamic clock adjustment. To alleviate the issue of unused dynamic timing margins, the clock period of the processor is adjusted on a cycle-by-cycle level, based on the instruction ty ...

Ieee2016