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Concept

Memory bank

Publications associées (9)

EdgeAI-Aware Design of In-Memory Computing Architectures

Marco Antonio Rios

Driven by the demand for real-time processing and the need to minimize latency in AI algorithms, edge computing has experienced remarkable progress. Decision-making AI applications stand out for their heavy reliance on data-centric operations, predominantl ...

EPFL2024

Miss-Optimized Memory Systems: Turning Thousands of Outstanding Misses into Reuse Opportunities

Mikhail Asiatici

Even if Dennard scaling came to an end fifteen years ago, Moore' s law kept fueling an exponential growth in compute performance through increased parallelization. However, the performance of memory and, in particular, Dynamic Random Access Memory (DRAM), ...

EPFL2021

Advances in computational and statistical diffusion MRI

Alessandro Daducci

Computational methods are crucial for the analysis of diffusion magnetic resonance imaging (MRI) of the brain. Computational diffusion MRI can provide rich information at many size scales, including local microstructure measures such as diffusion anisotrop ...

2019

DynaBurst: Dynamically Assemblying DRAM Bursts over a Multitude of Random Accesses

Paolo Ienne, Mikhail Asiatici

The effective bandwidth of the FPGA external memory, usually DRAM, is extremely sensitive to the access pattern. Nonblocking caches that handle thousands of outstanding misses (miss-optimized memory systems) can dynamically improve bandwidth utilization wh ...

IEEE2019

Universally Scalable Concurrent Data Structures

Tudor Alexandru David

The increase in the number of cores in processors has been an important trend over the past decade. In order to be able to efficiently use such architectures, modern software must be scalable: performance should increase proportionally to the number of all ...

EPFL2017

Network-on-chip using request and reply trees for low-latency processor-memory communication

Babak Falsafi, Boris Robert Grot

A Network-On-Chip (NOC) organization comprises a die having a cache area and a core area, a plurality of core tiles arranged in the core area in a plurality of subsets, at least one cache memory bank arranged in the cache area, whereby the at least one cac ...

2014

Towards Multi-Fabric 3D Integration Architectures

Panagiotis Athanasopoulos

The main aim of this thesis is to examine the advantages of 3D stacking applied to microprocessors and related integrated microprocessor systems in the architectural level. In the succession of years microprocessors are aiming towards lower power consumpti ...

EPFL2012

Self-Aligned 3D Chip Integration Technology and Through-Silicon Serial Data Transmission

Fengda Sun

The emerging three-dimensional (3D) integration technology is expected to lead to an industry paradigm shift due to its tremendous benefits. Intense research activities are going on about technology, simulation, design, and product prototypes. This thesis ...

EPFL2011

Performance and Energy Trade-offs Analysis of L2 on-Chip Cache Architectures for Embedded MPSoCs

Martino Ruggiero, Mohamed Mostafa Sabry Aly, Pablo Garcia del Valle

On-chip memory organization is one of the most important aspects that can influence the overall system behavior in multi-processor systems. Following the trend set by high-performance processors, high-end embedded cores are moving from single-level on chip ...

2010