Publications related to Nanostencil-based lithography for silicon nanowires fabrication

Related publications (7)

Unraveling Interdiffusion Phenomena and the Role of Nanoscale Diffusion Barriers in the Copper-Gold System

Diffusion is one of the most fundamental concepts in materials science, playing a pivotal role in materials synthesis, forming, and degradation. Of particular importance is solid state interdiffusion of metals which defines the usable parameter space for m ...

AMER CHEMICAL SOC2024

Theoretical Studies of Nanowire Ion-Sensitive Field Effect Transistor

Jean-Michel Sallese, Ashkhen Yesayan

The operation principle of a semiconductor nanowire (NW) ion-sensitive field-effect transistor (ISFET), denoted for pH sensing, is studied within the framework of this work. The physical processes in the system are mathematically modelled and presented in ...

PLEIADES PUBLISHING INC2021

Increased Photoconductivity Lifetime in GaAs Nanowires by Controlled n-Type and p-Type Doping

Anna Fontcuberta i Morral, Federico Matteini, Alberto Casadei, Fauzia Jabeen

Controlled doping of GaAs nanowires is crucial for the development of nanowire-based electronic and optoelectronic devices. Here, we present a noncontact method based on time resolved terahertz photoconductivity for assessing n- and p-type doping efficienc ...

American Chemical Society2016

Cracking the Si Shell Growth in Hexagonal GaP-Si Core-Shell Nanowires

Anna Fontcuberta i Morral, Sonia Conesa Boj

Semiconductor nanowires have increased the palette of possible heterostructures thanks to their more effective strain relaxation. Among these core shell heterostructures are much more sensitive to strain than axial Ones. It is now accepted that the formati ...

American Chemical Society2015

The high-mobility bended n-channel silicon nanowire transistor

Mihai Adrian Ionescu, Didier Bouvet, Kirsten Emilie Moselund, Vincent Pott, Luca De Michielis, Mohammad Najmzadeh

This work demonstrates a method for incorporating strain in silicon nanowire gate-all-around (GAA) n-MOSFETs by oxidation-induced bending of the nanowire channel and reports on the resulting improvement in device performance. The variation in strain measur ...

Institute of Electrical and Electronics Engineers2010

Fabrication and Characterization of Gate-All-Around Silicon Nanowires on Bulk Silicon

Mihai Adrian Ionescu, Didier Bouvet, Kirsten Emilie Moselund, Vincent Pott, Luca De Michielis

This paper reports on the top-down fabrication and electrical performance of silicon nanowire (SiNW) gate-all-around (GAA) n-type and p-type MOSFET devices integrated on bulk silicon using a local-silicon-on-insulator (SOI) process. The proposed local-SOI ...

2008

Gate-all-around silicon nanowires for hybrid single electron transistor/CMOS applications

Vincent Pott

Scaling of semiconductor devices has pushed CMOS devices close to fundamental limits. The remarkable success story of Moore's law during the last 40 years, predicting the evolution of electronic device performances related to miniaturization, has always be ...

EPFL2007