MOMS-based Programmable Sampling Rate Converters

Chat with Graph Search

Ask any question about EPFL courses, lectures, exercises, research, news, etc. or try the example questions below.

DISCLAIMER: The Graph Chatbot is not programmed to provide explicit or categorical answers to your questions. Rather, it transforms your questions into API requests that are distributed across the various IT services officially administered by EPFL. Its purpose is solely to collect and recommend relevant references to content that you can explore to help you answer your questions.

The pervasive adoption of field-programmable gate arrays (FPGAs) in both cyber-physical systems and the cloud has raised many security issues. Being integrated circuits, FPGAs are susceptible to fault and power side-channel attacks, which require physical ...

Field-programmable gate arrays (FPGAs) have become critical components in many cloud computing platforms. These devices possess the fine-grained parallelism and specialization needed to accelerate applications ranging from machine learning to networking an ...

Cloud computing environments increasingly provision FPGAs because of their fine-grained, highly parallel, and flexible hardware architecture. The availability of FPGAs in the cloud fueled research on the security risks associated with exposing FPGA fabric ...

We identified that in modern commercial FPGAs, routing signals from the general interconnect to the configurable logic blocks (CLBs) through a very sparse input interconnect block (IIB) represents a significant runtime bottleneck. This is despite academic ...

Side-channel disassembly attacks recover CPU instructions from power or electromagnetic side-channel traces measured during code execution. These attacks typically rely on physical access, proximity to the victim device, and high sampling rate measuring in ...

In this work, we develop timing-driven CAD support for FPGA architectures with direct connections between LUTs. We do so by proposing an efficient ILP-based detailed placer, which moves a carefully selected subset of LUTs from their original positions, so ...

Field-programmable gate arrays (FPGAs) combine hardware reconfigurability with a high degree of parallelism. Consequently, FPGAs offer performance gains and power savings for many applications. A recent trend has been to leverage the hardware versatility o ...

FPGAs are proving useful and attractive for many applications, thanks to their hardware reconfigurability, low power, and high-degree of parallelism. As a result, modern embedded systems are often based on systems-on-chip (SoCs), where CPUs and FPGAs share ...

Model compression techniques have lead to a reduction of size and number of computations of Deep Learning models. However, techniques such as pruning mostly lack of a real co-optimization with hardware platforms. For instance, implementing unstructured pru ...

Novel applications have triggered significant changes at the system level of FPGA architecture design, such as the introduction of embedded VLIW processor arrays and hardened NoCs. However, the routing architecture of the soft logic fabric has largely rema ...

Since their inception more than thirty years ago, field-programmable gate arrays (FPGAs) have been widely used to implement a myriad of applications from different domains. As a result of their low-level hardware reconfigurability, FPGAs have much faster d ...

The research community has been making significant progress in hardware implementation, numerical computing and algorithm development for optimization-based control. However, there are two key challenges that still have to be overcome for optimization-base ...

The increasing luminosity in HEP (High Energy Physics) colliders demands trigger systems to be more selective. First, more information from the detector is routed to the trigger system. Second, larger parts of this information are processed together. These ...

Threshold Implementations have become a popular generic technique to construct circuits resilient against power analysis attacks.In this paper, we look to devise efficient threshold circuits for the lightweight block cipher family SKINNY. The only threshol ...

The exponential growth in computing power and multimedia services has caused a tremendous increase in data traffic in recent years. This increase in data traffic brings a strong demand for data bandwidth of electrical input/output (I/O) links and pushes th ...

Even if Dennard scaling came to an end fifteen years ago, Moore' s law kept fueling an exponential growth in compute performance through increased parallelization. However, the performance of memory and, in particular, Dynamic Random Access Memory (DRAM), ...

The idea of introducing dedicated, fast paths between certain FPGA elements in order to reduce delay is neither new nor particularly hard to come up with. What is less obvious, however, is how to put such paths to actual use. In this work, we propose an ef ...

In this work, we present an automated approach for locating power-wasting attackers in shared FPGAs. In this approach, the FPGA shell is responsible for, first, placing the user designs and, second, inserting voltage sensors in a nonintrusive and adaptive ...

Recent works have demonstrated the possibility of extracting secrets from a cryptographic core running on an FPGA by means of remote power analysis attacks. To mount these attacks, an adversary implements a voltage fluctuation sensor in the FPGA logic, rec ...

The cameras are invented by imitating the human visual system to capture the scene. The camera technologies have been substantially advanced in recent years. 108 MP resolution with 100x hybrid zoom has become standard features for smartphone flagships. In ...

MOMS-based Programmable Sampling Rate Converters

Chat with Graph Search

Evaluating, Exploiting, and Hiding Power Side-Channel Leakage of Remote FPGAs

A Visionary Look at the Security of Reconfigurable Cloud Computing

Practical Implementations of Remote Power Side-Channel and Fault-Injection Attacks on Multitenant FPGAs

IIBLAST: Speeding Up Commercial FPGA Routing by Decoupling and Mitigating the Intra-CLB Bottleneck

Instruction-Level Power Side-Channel Leakage Evaluation of Soft-Core CPUs on Shared FPGAs

Detailed Placement for Dedicated LUT-Level FPGA Interconnect

DFAulted: Analyzing and Exploiting CPU Software Faults Caused by FPGA-Driven Undervolting Attacks

FPGA-to-CPU Undervolting Attacks

Structured and tiled-based pruning of Deep Learning models targeting FPGA implementations

NetCracker: A Peek into the Routing Architecture of Xilinx 7-Series FPGAs

Synthesizing General-Purpose Code Into Dynamically Scheduled Circuits

Optimization Methods for Control: From Embedded Programmable Hardware to Data-Driven Process Optimization

Low-Latency High-Bandwidth Circuit and System Design for Trigger Systems in High Energy Physics

Improving First-Order Threshold Implementations of SKINNY

Energy-Efficient Design Techniques for High-Speed Wireline Serial Links

Miss-Optimized Memory Systems: Turning Thousands of Outstanding Misses into Reuse Opportunities

Timing-Driven Placement for FPGA Architectures with Dedicated Routing Paths

Nonintrusive and Adaptive Monitoring for Locating Voltage Attacks in Virtualized FPGAs

Are Cloud FPGAs Really Vulnerable to Power Analysis Attacks?

Beyond Cameras: Real-Time High-Resolution 3D and Panoramic MultiView Vision Systems with Their Applications