A Complete Network-On-Chip Emulation Framework

Chat with Graph Search

Ask any question about EPFL courses, lectures, exercises, research, news, etc. or try the example questions below.

DISCLAIMER: The Graph Chatbot is not programmed to provide explicit or categorical answers to your questions. Rather, it transforms your questions into API requests that are distributed across the various IT services officially administered by EPFL. Its purpose is solely to collect and recommend relevant references to content that you can explore to help you answer your questions.

Verification and testing of hardware heavily relies on cycle-accurate simulation of RTL. As single-processor performance is growing only slowly, conventional, single-threaded RTL simulation is becoming impractical for increasingly complex chip designs and ...

Embedded memories occupy an increasingly dominant part of the area and power budgets of modern systems-on-chips (SoCs). Multi-ported embedded memories, commonly used by media SoCs and graphical processing units, occupy even more area and consume higher pow ...

The demise of Moore's Law and Dennard scaling has resulted in diminishing performance gains for general-purpose processors, and so has prompted a surge in academic and commercial interest for hardware accelerators. Specialized hardware has already redefine ...

Today's continued increase in demand for processing power, despite the slowdown of Moore's law, has led to an increase in processor count, which has resulted in energy consumption and distribution problems. To address this, there is a growing trend toward ...

In this work, we propose an open-hardware low-power coarse-grained reconfigurable array connected to a lightweight microcontroller and enclosed in an application mapping framework. The latter provides complete support to configure kernels in the reconfigur ...

Vision systems built around conventional image sensors have to read, encode and transmit large quantities of pixel information, a majority of which is redundant. As a result, new computational imaging sensor architectures were developed to preprocess the r ...

Side-channel disassembly attacks recover CPU instructions from power or electromagnetic side-channel traces measured during code execution. These attacks typically rely on physical access, proximity to the victim device, and high sampling rate measuring in ...

Modern hardware is increasingly complex, requiring increasing effort to understand in order to carefully engineer systems for optimal performance and effective utilization. Moreover, established design principles and assumptions are not portable to modern ...

The performance of programs executed on heterogeneous parallel platforms largely depends on the design choices regarding how to partition the processing on the various different processing units. In other words, it depends on the assumptions and parameters ...

FPGAs are proving useful and attractive for many applications, thanks to their hardware reconfigurability, low power, and high-degree of parallelism. As a result, modern embedded systems are often based on systems-on-chip (SoCs), where CPUs and FPGAs share ...

Field-programmable gate arrays (FPGAs) combine hardware reconfigurability with a high degree of parallelism. Consequently, FPGAs offer performance gains and power savings for many applications. A recent trend has been to leverage the hardware versatility o ...

The increasing power density in modern high-performance multi-processor system-on-chip (MPSoC) is fueling a revolution in thermal management. On the one hand, thermal phenomena are becoming a critical concern, making accurate and efficient simulation a nec ...

Collective spin excitations can propagate in magnetically ordered materials in the form of waves. These so-called spin waves (SWs) or magnons are promising for low-power beyond-CMOS information processing, which does not rely anymore on the lossy movement ...

Heterogeneous processing platforms combining in various architectures CPUs, GPUs, and programmable logic, are continuously evolving providing at each generation higher theoretical levels of computing performance. However, the challenge of how efficiently s ...

Deeply-scaled three-dimensional (3D) Multi-Processor Systems-on-Chip (MPSoCs) enable high performance and massive communication bandwidth for next-generation computing. However, as process nodes shrink, temperature-dependent leakage dramatically increases, ...

Embedded systems are deployed in security critical environments and have become a prominent target for remote attacks. Microcontroller-based systems (MCUS) are particularly vulnerable due to a combination of limited resources and low level programming whic ...

Moving from steam and waterpower, electricity and assembly lines, and computerization, to the adoption of cyber-physical systems, the Internet of Things and the Internet of Systems executed as intelligent machines, the world now dives into a new era called ...

The broad applications of ultrawide-band signals and terahertz waves in quantum measurements, imaging and sensing techniques, advanced biological treatments, and very-high-data-rate communications have drawn extensive attention to ultrafast electronics. In ...

Albeit very appealing, FPGA multitenancy in the cloud computing environment is currently on hold due to a number of recently discovered vulnerabilities to side-channel attacks and covert communication. In this work, we successfully demonstrate a new attack ...

In my thesis, I reveal several already-existing and emerging challenges in multi-objective management of multiprocessor systems, and address them through novel solutions, from heuristics to RL, depending on the complexity of the problem. Conventional multi ...

A Complete Network-On-Chip Emulation Framework

Chat with Graph Search

Highly Parallel RTL Simulation

Multi-Ported GC-eDRAM Bitcell with Dynamic Port Configuration and Refresh Mechanism

Building Chips Faster: Hardware-Compiler Co-Design for Accelerated RTL Simulation

Compilation and Design Space Exploration of Dataflow Programs for Heterogeneous CPU-GPU Platforms

An Open-Hardware Coarse-Grained Reconfigurable Array for Edge Computing

Computational Imaging SPAD Cameras

Instruction-Level Power Side-Channel Leakage Evaluation of Soft-Core CPUs on Shared FPGAs

Chaosity: Understanding Contemporary NUMA-architectures

Performance Estimation of High-Level Dataflow Program on Heterogeneous Platforms by Dynamic Network Execution

FPGA-to-CPU Undervolting Attacks

DFAulted: Analyzing and Exploiting CPU Software Faults Caused by FPGA-Driven Undervolting Attacks

3D-ICE 3.0: efficient nonlinear MPSoC thermal simulation with pluggable heat sink models

Magnonic crystals with reconfigurable magnetic defects for spin-based microwave electronics

Programming Heterogeneous CPU-GPU Systems by High-Level Dataflow Synthesis

Towards Deeply Scaled 3D MPSoCs with Integrated Flow Cell Array Technology

mu RAI: Securing Embedded Systems with Return Address Integrity

Broadening artificial intelligence education in K-12: Where to Start?

Nanoplasma-enabled picosecond switches for ultrafast electronics

X-Attack: Remote Activation of Satisfiability Don’t-Care Hardware Trojans on Shared FPGAs

Multi-Objective Management of Multiprocessor Systems: From Heuristics to Reinforcement Learning