Improving Circuit Mapping Performance Through MIG-based Synthesis for Carry Chains

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Electronic devices play an irreplaceable role in our lives. With the tightening time to market, exploding demand for computing power, and continuous desire for smaller, faster, less energy-consuming, and lower-cost chips, computer-aided design for electron ...

Verification and testing of hardware heavily relies on cycle-accurate simulation of RTL. As single-processor performance is growing only slowly, conventional, single-threaded RTL simulation is becoming impractical for increasingly complex chip designs and ...

We study the proof theory and algorithms for orthologic, a logical system based on ortholattices, which have shown practical relevance in simplification and normalization of verification conditions. Ortholattices weaken Boolean algebras while having polyno ...

Rapid single-flux quantum (RSFQ) is one of the most advanced and promising superconducting logic families, offering exceptional energy efficiency and speed. RSFQ technology requires delay registers (DFFs) and splitter cells to satisfy the path-balancing an ...

We study quantifiers and interpolation properties in ortho- logic, a non-distributive weakening of classical logic that is sound for formula validity with respect to classical logic, yet has a quadratic-time decision procedure. We present a sequent-based p ...

Logic rewriting is a powerful optimization technique that replaces small sections of a Boolean network with better implementations. Typically, exact synthesis is used to compute optimum replacement on-the-fly, with possible support for Boolean don't cares. ...

Machine learning algorithms such as Convolutional Neural Networks (CNNs) are characterized by high robustness towards quantization, supporting small-bitwidth fixed-point arithmetic at inference time with little to no degradation in accuracy. In turn, small ...

Coarse-Grain Reconfigurable Arrays (CGRAs) represent emerging low-power architectures designed to accelerate Compute-Intensive Loops (CILs). The effectiveness of CGRAs in providing acceleration relies on the quality of mapping: how efficiently the CIL is c ...

Factored form is a powerful multi-level representation of a Boolean function that readily translates into an implementation of the function in CMOS technology. In particular, the number of literals in a factored form correlates strongly with the number of ...

State-of-the-art sensors for measuring FPGA voltage fluctuations are time-to-digital converters (TDCs). They allow detecting voltage fluctuations in the order of a few nanoseconds. The key building component of a TDC is a delay line, typically implemented ...

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By supporting the access of multiple memory words at the same time, Bit-line Computing (BC) architectures allow the parallel execution of bit-wise operations in-memory. At the array periphery, arithmetic operations are then derived with little additional o ...

The pervasive adoption of field-programmable gate arrays (FPGAs) in both cyber-physical systems and the cloud has raised many security issues. Being integrated circuits, FPGAs are susceptible to fault and power side-channel attacks, which require physical ...

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We identified that in modern commercial FPGAs, routing signals from the general interconnect to the configurable logic blocks (CLBs) through a very sparse input interconnect block (IIB) represents a significant runtime bottleneck. This is despite academic ...

Improving Circuit Mapping Performance Through MIG-based Synthesis for Carry Chains

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Contemporary Logic Synthesis: with an Application to AQFP Circuit Optimization

Highly Parallel RTL Simulation

Orthologic with Axioms

Algebraic and Boolean Methods for SFQ Superconducting Circuits

Interpolation and Quantifiers in Ortholattices

Scalable Logic Rewriting Using Don’t Cares

DBFS: Dynamic Bitwidth-Frequency Scaling for Efficient Software-defined SIMD

SAT-based Exact Modulo Scheduling Mapping for Resource-Constrained CGRAs

Improving Standard-Cell Design Flow using Factored Form Optimization

RDS: FPGA Routing Delay Sensors for Effective Remote Power Analysis Attacks

2D Nanosystems: Applications of 2D Semiconductors for In-Memory Computing

Automating the Design of Programmable Interconnect for Reconfigurable Architectures

Building Chips Faster: Hardware-Compiler Co-Design for Accelerated RTL Simulation

Energy Efficient Logic and Memory Design With Beyond-CMOS Magnetoelectric Spin-Orbit (MESO) Technology Toward Ultralow Supply Voltage

Bit-Line Computing for CNN Accelerators Co-Design in Edge AI Inference

Evaluating, Exploiting, and Hiding Power Side-Channel Leakage of Remote FPGAs

Exploring brain-inspired multi-core heterogeneous hardware templates for low-power biomedical embedded systems

WarpAttack: Bypassing CFI through Compiler-Introduced Double-Fetches

MOD2IR: High-Performance Code Generation for a Biophysically Detailed Neuronal Simulation DSL

IIBLAST: Speeding Up Commercial FPGA Routing by Decoupling and Mitigating the Intra-CLB Bottleneck