Publication

Experimental setup and o-ring based μfluidic interface for suspended microchannel resonators

2017
Posters

Abstract

Existing solutions for suspended microchannel resonators packaging - Fluidic delivery (back-side) : PDMS or o-ring sealing - Vacuum encapsulation (front-side) : glass capping or o-ring sealing Our suspended microchannel resonators have inlets and outlets on the front-side - Fluidic delivery and vacuum must coexist : complete solutioon based on o-rings - Need for an intermediary connector, prototyped via stereolithography 3D printing, between the chip and the external equipment We developed a setup for temperature control and fluidic delivery

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2017
Posters

Abstract

Official source

Related concepts (12)

O-ring

An O-ring, also known as a packing or a toric joint, is a mechanical gasket in the shape of a torus; it is a loop of elastomer with a round cross-section, designed to be seated in a groove and compressed during assembly between two or more parts, forming a seal at the interface. The O-ring may be used in static applications or in dynamic applications where there is relative motion between the parts and the O-ring. Dynamic examples include rotating pump shafts and hydraulic cylinder pistons.

Front-side bus

The front-side bus (FSB) is a computer communication interface (bus) that was often used in Intel-chip-based computers during the 1990s and 2000s. The EV6 bus served the same function for competing AMD CPUs. Both typically carry data between the central processing unit (CPU) and a memory controller hub, known as the northbridge. Depending on the implementation, some computers may also have a back-side bus that connects the CPU to the cache. This bus and the cache connected to it are faster than accessing the system memory (or RAM) via the front-side bus.

Back-side bus

In personal computer microprocessor architecture, a back-side bus (BSB), or backside bus, was a computer bus used on early Intel platforms to connect the CPU to CPU cache memory, usually off-die L2. If a design utilizes it along with a front-side bus (FSB), it is said to use a dual-bus architecture, or in Intel's terminology Dual Independent Bus (DIB) architecture. The back-side bus architecture evolved when newer processors like the second-generation Pentium III began to incorporate on-die L2 cache, which at the time was advertised as Advanced Transfer Cache, but Intel continued to refer to the Dual Independent Bus till the end of Pentium III.