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A back-illuminated 3D-stacked single-photon avalanche diode in 45nm CMOS technology

Related publications (31)

Avalanche Microwave Noise Sources in Commercial 90-nm CMOS Technology

Christian Enz, Pierre-André Farine, Cyril Botteron, Gabriele Tasselli

This paper presents a microwave noise source implemented in a commercial CMOS technology. The circuit is based on the avalanche noise generated by both the source-to-bulk and the drain-to-bulk junctions in reverse breakdown. Two sources of different juncti ...

Institute of Electrical and Electronics Engineers2016

High-Voltage Tolerant Bi-State Self-Biasing Output Driver using Cascade Complementary Latches in Twin-well CMOS Technology

Scott Anthony Lindner

The design of a bi-state output buffer that can handle 5 times the supply voltage is presented. The use of self-biasing stacked devices driven by a cascade of complementary latches allows all devices to operate within the limits set by the technology, thus ...

Ieee2016

Co-design of ReRAM Passive Crossbar Arrays Integrated in 180nm CMOS Technology

Yusuf Leblebici, Giovanni De Micheli, Michele De Marchi, Davide Sacchetto, Jury Sandrini, Pierre-Emmanuel Julien Marc Gaillardon, Tugba Demirci, Maxime Victor Thammasack, Marios Barlas

This work presents the co-integration of resistive random access memory crossbars within a 180nm Read-Write CMOS chip. TaOx-based ReRAMs have been fabricated and characterized with materials and process steps compatible with the CMOS Back-End-of ...

Institute of Electrical and Electronics Engineers2016

Noise Reduction Techniques and Scaling Effects towards Photon Counting CMOS Image Sensors

Christian Enz, Assim Boukhayma

This paper presents an overview of the read noise in CMOS image sensors (CISs) based on four-transistors (4T) pixels, column-level amplification and correlated multiple sampling. Starting from the input-referred noise analytical formula, process level opti ...

Mdpi Ag2016

Double-Gate Negative-Capacitance MOSFET with PZT gate stack on Ultra-Thin Body SOI: an Experimentally Calibrated Simulation Study of Device Performance

Igor Stolichnov, Mihai Adrian Ionescu, Farzan Jazaeri, Ali Saeidi

In this work, we propose and investigate the high performance and low power design space of non-hysteretic negative capacitance MOSFETs for the 14nm node based on the calibrated simulations using an experimental gate stack with PZT ferroelectric to obtain ...

2016

Analysis and Characterization of Variability in Subthreshold Source-Coupled Logic Circuits

Alexandre Schmid, Yusuf Leblebici, Seyed Armin Tajalli, Mahsa Shoaran

This article explores the effect of device parameter variations on the performance of subthreshold source-coupled logic (STSCL) circuits. A test chip has been fabricated in a standard CMOS 90 nm technology to study the matching properties of STSCL circuits ...

2015

A 2.4-GHz low power polar transmitter for wireless body area network applications

Christian Enz, Vladimir Kopta, Franz Xaver Pengg

A 2.4 GHz low power polar transmitter is proposed in this paper. A dynamic biasing circuit, controlled by a digital envelope signal, is used as a direct digital-to-RF envelope converter. It effectively linearizes the input-output characteristic of the over ...

Springer Verlag2014

Amorphous silicon enhanced metal-insulator-semiconductor contacts for silicon solar cells

Aïcha Hessler-Wyser, Bénédicte Demaurex, Stefaan De Wolf

Carrier recombination at the metal-semiconductor contacts has become a significant obstacle to the further advancement of high-efficiency diffused-junction silicon solar cells. This paper provides the proof-of-concept of a procedure to reduce contact recom ...

American Institute of Physics2014

A Geiger Mode APD fabricated in Standard 65nm CMOS Technology

Edoardo Charbon, Hyungjune Yoon

We present the first avalanche photodiode (APD) successfully fabricated in standard 65nm CMOS technology. The APD operates both in proportional and Geiger mode at -60C to +60C temperature range. The device comprises an octagonal n+p-well junction surrounde ...

2013

Single-layer MoS₂ : Electronics in Two Dimensions

Branimir Radisavljevic

This thesis explores the electronic properties of one layered transition-metal dichalcogenide – single-layer MoS2, and demonstrates the first transistors and integrated circuits with characteristics that outperform graphene electronics in many aspects and ...

EPFL2013

Design Methodologies and CAD for Emerging Nanotechnologies

Shashi Kanth Bobba

With technology scaling reaching the fundamental limits of Si-CMOS in the near future, the semiconductor industry is in quest for innovation from various disciplines of integrated circuit (IC) design. At a fundamental level, technology forms the main drive ...

EPFL2013