EPICURE : A Partitioning and CoDesign Framework For Reconfigurable Computing

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This article outlines the advancements made in broadening the application scope of the OpenMC neutron transport code to include thermohydraulic coupling and nuclear data uncertainty propagation. These developments primarily involve the incorporation of the ...

Machine learning algorithms such as Convolutional Neural Networks (CNNs) are characterized by high robustness towards quantization, supporting small-bitwidth fixed-point arithmetic at inference time with little to no degradation in accuracy. In turn, small ...

Electronic devices play an irreplaceable role in our lives. With the tightening time to market, exploding demand for computing power, and continuous desire for smaller, faster, less energy-consuming, and lower-cost chips, computer-aided design for electron ...

The rapid progress in the field of deep learning has had a significant impact on protein design. Deep learning methods have recently produced a breakthrough in protein structure prediction, leading to the availability of high-quality models for millions of ...

We identified that in modern commercial FPGAs, routing signals from the general interconnect to the configurable logic blocks (CLBs) through a very sparse input interconnect block (IIB) represents a significant runtime bottleneck. This is despite academic ...

Formally verifying the correctness of software network functions (NFs) is necessary for network reliability, yet existing techniques require full source code and mandate the use of specific data structures. We describe an automated technique to verify NF b ...

The hardware complexity of modern machines makes the design of adequate programming models crucial for jointly ensuring performance, portability, and productivity in high-performance computing (HPC). Sequential task-based programming models paired with adv ...

Field-programmable gate arrays (FPGAs) combine hardware reconfigurability with a high degree of parallelism. Consequently, FPGAs offer performance gains and power savings for many applications. A recent trend has been to leverage the hardware versatility o ...

Formal verification of real-world software systems remains challenging for a number of reasons, including lack of automation, friction in specifying properties, and limited support for the diverse programming paradigms used in industry. In this thesis we m ...

Model-checking intends to verify whether a property is satisfied by a model, or not. Model-checking of high-level models, e.g. SysML models, usually first requires a model transformation to a low level formal specification. The present papers proposes a ne ...

Since their inception more than thirty years ago, field-programmable gate arrays (FPGAs) have been widely used to implement a myriad of applications from different domains. As a result of their low-level hardware reconfigurability, FPGAs have much faster d ...

The increasing luminosity in HEP (High Energy Physics) colliders demands trigger systems to be more selective. First, more information from the detector is routed to the trigger system. Second, larger parts of this information are processed together. These ...

Background: Coronary artery disease (CAD) is in part genetically determined. Aging is accentuated in people with human immunodeficiency virus (HIV) (PLWH). It is unknown whether genetic CAD event prediction in PLWH is improved by applying individual polyge ...

The research community has been making significant progress in hardware implementation, numerical computing and algorithm development for optimization-based control. However, there are two key challenges that still have to be overcome for optimization-base ...

Software network functions (NFs), such as a network address translator, load balancer, or proxy, promise to bring flexibility and rapid innovation to computer networks and to reduce operational costs. However, continuous updates and flexibility typically c ...

FPGA routing is one of the most time-consuming steps of FPGA compilation, often preventing fast edit-compile-test cycles in prototyping and development. There have been attempts to accelerate FPGA routing using algorithmic improvements, multi-core or multi ...

A central task in high-level synthesis is scheduling: the allocation of operations to clock cycles. The classic approach to scheduling is static, in which each operation is mapped to a clock cycle at compile-time, but recent years have seen the emergence o ...

In this paper, the hardware acceleration of a tone-mapping algorithm for High-Dynamic-Range image processing is presented. Starting from the C++ source code, High-Level Synthesis has been performed using Xilinx SDSoC for a Xilinx Zynq SoC device. After an ...

Spurred by the recent advancements in Computer-Aided Design (CAD), Integral Mechanical Attachment (IMA) technique has been resurrected. Using IMAs, connections between timber elements are established through their form, instead of using additional connecto ...

Biomolecular computing is the field of engineering where computation, storage, communication, and coding are obtained by exploiting interactions between biomolecules, especially DNA, RNA, and enzymes. They are a promising solution in a long-term vision, br ...

EPICURE : A Partitioning and CoDesign Framework For Reconfigurable Computing

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Tool Developments in the OpenMC Code: Correlated Sampling and Transient Fission Matrix Approach Coupled to OpenFOAM

DBFS: Dynamic Bitwidth-Frequency Scaling for Efficient Software-defined SIMD

Contemporary Logic Synthesis: with an Application to AQFP Circuit Optimization

A new age in protein design empowered by deep learning

IIBLAST: Speeding Up Commercial FPGA Routing by Decoupling and Mitigating the Intra-CLB Bottleneck

Automated Verification of Network Function Binaries

Decentralized in-order execution of a sequential task-based code for shared-memory architectures

DFAulted: Analyzing and Exploiting CPU Software Faults Caused by FPGA-Driven Undervolting Attacks

Scaling Language Features for Program Verification

Direct Model-checking of SysML Models

Synthesizing General-Purpose Code Into Dynamically Scheduled Circuits

Low-Latency High-Bandwidth Circuit and System Design for Trigger Systems in High Energy Physics

Coronary Artery Disease-Associated and Longevity-Associated Polygenic Risk Scores for Prediction of Coronary Artery Disease Events in Persons Living With Human Immunodeficiency Virus: The Swiss HIV Cohort Study

Optimization Methods for Control: From Embedded Programmable Hardware to Data-Driven Process Optimization

Verification of Software Network Functions with No Verification Expertise

FPGA-Assisted Deterministic Routing for FPGAs

Combining Dynamic & Static Scheduling in High-level Synthesis

Hardware Acceleration of HDR-Image Tone Mapping on an FPGA-CPU Platform Through High-Level Synthesis

Mechanical Characterization of Integrally-Attached Timber Plate Structures: Experimental studies and macro modeling technique

Biosensors for Bimolecular Computing: a Review and Future Perspectives