Publications related to A 5.35 mm2 10GBASE-T Ethernet LDPC Decoder Chip in 90 nm CMOS

Related publications (29)

A Generalized Adjusted Min-Sum Decoder for 5G LDPC Codes: Algorithm and Implementation

Andreas Peter Burg, Alexios Konstantinos Balatsoukas Stimming, Yifei Shen, Yuqing Ren, Hassan Harb

5G New Radio (NR) has stringent demands on both performance and complexity for the design of low-density parity-check (LDPC) decoding algorithms and corresponding VLSI implementations. Furthermore, decoders must fully support the wide range of all 5G NR bl ...

Ieee-Inst Electrical Electronics Engineers Inc2024

High-Throughput and Flexible Belief Propagation List Decoder for Polar Codes

Andreas Peter Burg, Alexios Konstantinos Balatsoukas Stimming, Yifei Shen, Yuqing Ren, Andreas Toftegaard Kristensen, Leyu Zhang

Due to its high parallelism, belief propagation (BP)decoding is amenable to high-throughput applications and thusrepresents a promising solution for the ultra-high peak datarate required by future communication systems. To bridge theperformance gap compare ...

Ieee-Inst Electrical Electronics Engineers Inc2024

On Speed and Advantage : Results in Information Velocity and Monitoring Problems

Reka Inovan

Information theory has allowed us to determine the fundamental limit of various communication and algorithmic problems, e.g., the channel coding problem, the compression problem, and the hypothesis testing problem. In this work, we revisit the assumptions ...

EPFL2024

EdgeAI-Aware Design of In-Memory Computing Architectures

Marco Antonio Rios

Driven by the demand for real-time processing and the need to minimize latency in AI algorithms, edge computing has experienced remarkable progress. Decision-making AI applications stand out for their heavy reliance on data-centric operations, predominantl ...

EPFL2024

Highly Parallel RTL Simulation

Seyedmahyar Emami

Verification and testing of hardware heavily relies on cycle-accurate simulation of RTL. As single-processor performance is growing only slowly, conventional, single-threaded RTL simulation is becoming impractical for increasingly complex chip designs and ...

EPFL2024

Low Power LDPC Decoding by Reliable Voltage Down-Scaling

Andreas Peter Burg

Low-Density Parity-Check (LDPC) decoder is among the power hungry building blocks of wireless communication systems. Voltage scaling down to Near-Threshold (NT) voltages substantially improves energy efficiency, in theory up 10x. However, tuning the voltag ...

IEEE2023

Computational Imaging SPAD Cameras

Andrei Ardelean

Vision systems built around conventional image sensors have to read, encode and transmit large quantities of pixel information, a majority of which is redundant. As a result, new computational imaging sensor architectures were developed to preprocess the r ...

EPFL2023

A 0.21-ps FOM Capacitor-Less Analog LDO with Dual-Range Load Current for Biomedical Applications

Yasemin Engür, Mahsa Shoaran

This paper presents an output capacitor-less low-dropout regulator (LDO) with a bias switching scheme for biomedical applications with dual-range load currents. Power optimization is crucial for systems with multiple activation modes such as neural interfa ...

ArXiv2023

Analysis of the influence of errors in DNA-based image coding

Touradj Ebrahimi, Michela Testolina, Davi Nachtigall Lazzarotto

In the last decade, DNA has been increasingly investigated as an alternative medium for cold data storage, presenting several advantages over standard hard drives such as a higher density, longer lifespan and lower energy consumption. However, such coding ...

2023

Semiconductor-based device architectures in multimaterial fibers

William Nicolas Duncan Esposito

Semiconductor materials have given rise to today's digital technology and consumer electronics. Widespread adoption is closely linked to the ability to process and integrate them in devices at scale. Where flexibility and large surfaces are required, such ...

EPFL2023

Green Cryptography and Other Optimisations

Andrea Felice Caforio

The spectral decomposition of cryptography into its life-giving components yields an interlaced network of tangential and orthogonal disciplines that are nonetheless invariably grounded by the same denominator: their implementation on commodity computing p ...

EPFL2023

Exploring brain-inspired multi-core heterogeneous hardware templates for low-power biomedical embedded systems

Benoît Walter Denkinger

The miniaturization of integrated circuits (ICs) and their higher performance and energy efficiency, combined with new machine learning algorithms and applications, have paved the way to intelligent, interconnected edge devices. In the medical domain, they ...

EPFL2023

An All-Digital 1 Mbps, 57 pJ/bit Bluetooth Low Energy (BLE) Backscatter ASIC in 65 nm CMOS

James Daniel Rosenthal

We present an all-digital application specific integrated circuit (ASIC) that implements Bluetooth Low Energy (BLE)-compatible backscatter communication. The ASIC was fabricated in a 65 nm CMOS process and occupies an active area of 0.12 mm(2) while consum ...

IEEE2022

Ultra-High-Throughput EMS NB-LDPC Decoder with Full-Parallel Node Processing

Hassan Harb

This paper presents an ultra-high-throughput decoder architecture for NB-LDPC codes based on the Hybrid Extended Min-Sum algorithm. We introduce a new processing block that updates a check node and its associated variable nodes in a fully pipelined way, th ...

SPRINGER2022

Secret Key Generation Using Short Blocklength Polar Coding Over Wireless Channels

Yanina Yurina Shkel

This paper investigates the problem of secret key generation from correlated Gaussian random variables in the short blocklength regime. Short blocklengths are commonly employed in massively connected IoT sensor networks in 5G and beyond wireless systems. P ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2022

Symmetry in design and decoding of polar-like codes

Kirill Ivanov

The beginning of 21st century provided us with many answers about how to reach the channel capacity. Polarization and spatial coupling are two techniques for achieving the capacity of binary memoryless symmetric channels under low-complexity decoding algor ...

EPFL2022

On the Efficiency of Polar-Like Decoding for Symmetric Codes

Rüdiger Urbanke, Kirill Ivanov

The recently introduced polar codes constitute a breakthrough in coding theory due to their capacity-achieving property. This goes hand in hand with a quasilinear construction, encoding, and successive cancellation list decoding procedures based on the Plo ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2022

High-Performance CMOS SPAD-Based Sensors for Time-of-Flight PET Applications

Francesco Gramuglia

Detecting light, photon by photon, has been possible since the 1930s, with the invention of the photomultiplier tube (PMT). However, it is only since the 1970s, that solid-state single-photon detectors have emerged and only since 2003 that a new technology ...

EPFL2022

Full System Exploration of On-Chip Wireless Communication on Many-Core Architectures

David Atienza Alonso, Giovanni Ansaloni, Marina Zapater Sancho, Yasir Mahmood Qureshi, Joshua Alexander Harrison Klein, Rafael Medina Morillas

In order to develop sustainable and more powerful information technology (IT) infrastructures, the challenges posed by the "memory wall" are critical for the design of high-performance and high-efficiency many-core computing systems. In this context, recen ...

IEEE2022

Optima Age Over Erasure Channels

Emre Telatar, Rajai Nasser, Elie Najm

Previous works on age of information and erasure channels have dealt with specific models and computed the average age or average peak age for certain settings. In this paper, given a source that produces a letter every T-s seconds and an erasure channel t ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2022