Towards a Unified Top-Down Design Flow for Fully-Differential Logic Blocks with Improved Speed and Noise Immunity

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Towards a Unified Top-Down Design Flow for Fully-Differential Logic Blocks with Improved Speed and Noise Immunity

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Electronic readout of DNA amplification in nanoliter chambers. Strategies towards highly parallel semiconductor-based nucleic acid amplification testing

Radiation Hardness of MALTA2, a Monolithic Active Pixel Sensor for Tracking Applications

Enablers for Overcurrent Capability of Silicon-Carbide-Based Power Converters: An Overview

Temperature Impact on Remote Power Side-Channel Attacks on Shared FPGAs

Thermal and Power-Aware Run-Time Performance Management of 3D MPSoCs with Integrated Flow Cell Arrays

A Deep-Learning Approach to Side-Channel Based CPU Disassembly at Design Time

A new versatile hybrid MEMS technology for high sensitivity, fluid proof sensing applications

Thermal and Voltage-Aware Performance Management of 3D MPSoCs with Flow Cell Arrays and Integrated SC Converters

A 500 x 500 Dual-Gate SPAD Imager With 100% Temporal Aperture and 1 ns Minimum Gate Length for FLIM and Phasor Imaging Applications

An All-Digital 1 Mbps, 57 pJ/bit Bluetooth Low Energy (BLE) Backscatter ASIC in 65 nm CMOS

Source Reconstruction Method Using Phase-Less Magnetic Near-Field Measurements: Application of the Method of Moment with Roof-Top Basis Functions