Publications related to Implementing Ultra-high-Value Floating Tunable CMOS Resistors

Related publications (18)

Ferroelectric gating of two-dimensional semiconductors for the integration of steep-slope logic and neuromorphic devices

Yingfen Wei, Mihai Adrian Ionescu, Jürgen Brugger, Ali Saeidi, Xia Liu, Carlotta Gastaldi, Sadegh Kamaei Bahmaei

The co-integration of logic switches and neuromorphic functions could be used to create new computing architectures with low power consumption and novel functionalities. Two-dimensional (2D) semiconductors and ferroelectric materials could be potentially u ...

NATURE PORTFOLIO2023

LiNiO Junction Gate for High-performance Enhancement-mode GaN Power Transistor

Taifang Wang

GaN metal-oxide-semiconductor high electron mobility transistors (MOS)HEMTs) offer outstanding properties for next-generation power electronics devices. The high conductivity, high voltage blocking capability, high operation frequency, and device-level int ...

EPFL2022

Heterostructure design and field management in III-N high-electron mobility electronic devices

Catherine Erine

III-N family of materials has offered multiple groundbreaking technologies in the field of optoelectronics and high-power radio-frequency (RF) devices. Blue light-emitting diodes (LEDs) have revolutionized low-energy lighting. Gallium nitride (GaN) RF mark ...

EPFL2021

Learning Temporary Block-Based Bidirectional Incongruity-Aware Correlation Filters for Efficient UAV Object Tracking

Yujie He

In the field of UAV object tracking, correlation filter based approaches have received lots of attention due to their computational efficiency. The methods learn filters by the ridge regression and generate response maps to distinguish the specified target ...

2020

Devices and Circuits Using Novel 2-D Materials: A Perspective for Future VLSI Systems

Giovanni De Micheli, Pierre-Emmanuel Julien Marc Gaillardon, Giovanni Vincenzo Resta

Here, we review the most recent developments in the field of 2-D electronics. We focus first on the synthesis of 2-D materials, discussing the different growth techniques currently available and assessing their strengths and weaknesses. Moreover, we descri ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2019

Co-integrated Subthermionic 2D/2D WSe2/SnSe2 Vertical Tunnel FET and WSe2 MOSFET on same flake: towards a 2D/2D vdW Dual-Transport Steep Slope FET

Mihai Adrian Ionescu, Matteo Cavalieri, Nicolò Oliva, Luca Capua

In this work we report the fabrication, co-integration and resulting performance of 2D/2D van der Waals (vdW) Vertical p-type Tunnel FETs and p-MOSFETs in a WSe2/SnSe2 material system. We demonstrate the best ever reported combined performance in terms of ...

IEEE2019

Light Confinement and Nonlinear Light-Matter Interaction in Semiconductor Photonic Crystal Cavities

Mohamed Sabry Abdel-Aliem Mohamed

The ability to control and manipulate light is a fundamental aspect that is at the very core of the development of integrated photonic circuits. It is desirable to achieve such control down to a scale that is comparable to or smaller than the wavelength of ...

EPFL2018

GaN-on-Si Quasi-Vertical Power MOSFETs

Elison de Nazareth Matioli, Riyaz Mohammed Abdul Khadar, Chao Liu

We demonstrate the first GaN vertical transistor on silicon, based on a 6.7-mu m-thick n-p-n heterostructure grown on 6-inch silicon substrate by metal organic chemical-vapor deposition. The devices consist of trench-gate quasi-vertical metal-oxide-semicon ...

Institute of Electrical and Electronics Engineers2018

Characterization and modeling of nanoscale MOSFET for ultra-low power RF IC design

Maria-Anna Chalkiadaki

The evolution and characteristics of the electronics is directly linked to the technological and societal progress. Today, there is a huge variety of electronic solutions offered, with the RF low-power systems, such as wireless sensor networks, wireless bo ...

EPFL2016

Cost-Effective Design of Mesh-of-Tree Interconnect for Multi-Core Clusters with 3-D Stacked L2 Scratchpad Memory

Giovanni De Micheli, Luca Benini

3-D integrated circuits (3-D ICs) offer a promising solution to overcome the scaling limitations of 2-D ICs. However, using too many through-silicon-vias (TSVs) pose a negative impact on 3-D ICs due to the large overhead of TSV (e.g., large footprint and l ...

Institute of Electrical and Electronics Engineers2015

Graphene Negative Differential Resistance Circuit With Voltage-Tunable High Performance at Room Temperature

Mihai Adrian Ionescu, Arnaud Magrez, Antonios Bazigos, Laurent Syavoch Bernard, Pankaj Sharma

We propose, fabricate, and experimentally demonstrate a circuit based on graphene field-effect transistors (GFETs) showing enhanced negative differential resistance (NDR) characteristics at room temperature. The proposed graphene NDR (GNDR) circuit consist ...

Institute of Electrical and Electronics Engineers2015

Tunable floating active inductor with internal offset reduction

Maher Kayal, Sidi-Rachid Cherkaoui, François Krummenacher, Marc Pastre, Laurent Fabre, Ira Nagel

Presented is a transistor-level implementation of a floating and tunable CMOS active inductor. It is based on the classical gyrator-C topology and is enhanced by adding an internal offset reduction mechanism to guarantee functionality also for unbalanced D ...

2012

A silicon model of the inner hair cell

Yusuf Leblebici

In this paper we present an electrical model of the inner hair cell based on an improved mathematical model. The model is implemented in silicon in the current domain using translinear circuits. It improves on previous models by taking into consideration t ...

2011

Integrated Circuits and Logic Operations Based on Single-Layer MoS2

Andras Kis, Branimir Radisavljevic

Logic circuits and the ability to amplify electrical signals form the functional backbone of electronics along with the possibility to integrate multiple elements on the same chip. The miniaturization of electronic circuits is expected to reach fundamental ...

2011

Inductive Power Link for a Wireless Cortical Implant With Two-Body Packaging

Catherine Dehollain, Michel Declercq, Kanber Mithat Silay

This paper presents an inductive power link for remote powering of a wireless cortical implant. The link includes a Class-E power amplifier, a gate driver, an inductive link, and an integrated rectifier. The coils of the inductive link are designed and opt ...

Institute of Electrical and Electronics Engineers2011

Global modeling strategy of parasitic coupled currents induced by minority-carrier propagation in semiconductor substrates

Maher Kayal, Jean-Michel Sallese, François Krummenacher, Marc Pastre, Fabrizio Lo Conte

This paper presents a modeling strategy to simulate the propagation of electrical perturbations induced by direct biasing of substrate junctions. Usually, this is done by identifying parasitic substrate devices such as bipolar transistors. However, mapping ...

2010

Fabrication and design of nanoscale regular circuits

Mohamed Haykel Ben Jamaa

During many decades, Moore's law, which predicts an exponential increase in performance of semiconductor logic circuits and memories and an exponential decrease in their area, has proven its universal validity. It also helped the semiconductor industry pre ...

EPFL2009

A Multilevel Power Converter with Integrated Storage for Particle Accelerators

Alfred Rufer

The PS accelerator (Proton-Synchrotron) at CERN (European Organization for Nuclear Research) is composed of one hundred magnets connected in series. During a cycle of 2.4 seconds, the active power at the magnets terminals varies from plus to minus 40 MW. A ...

2007