GC-eDRAM With Body-Bias Compensated Readout and Error Detection in 28-nm FD-SOI

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This paper presents an in-depth DC characterization of a 22 nm FDSOI CMOS technology down to deep cryogenic temperature, i.e., 2.95 K. The impact of the back-gate voltage (V-back) on device performance, i.e., threshold voltage (V-T) and carrier transport, ...

GC-eDRAM With Body-Bias Compensated Readout and Error Detection in 28-nm FD-SOI

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